[PATCH v2 3/3] ARM: dts: sam9x60: add rtt

[Claudiu Beznea]

Add RTT. Allong with it enable GBPR as it is requested by RTT.

Signed-off-by: Claudiu Beznea <claudiu.bez...@microchip.com>
---
 arch/arm/boot/dts/at91-sam9x60ek.dts | 9 +++++++++
 arch/arm/boot/dts/sam9x60.dtsi       | 7 +++++++
 2 files changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts 
b/arch/arm/boot/dts/at91-sam9x60ek.dts
index b484745bf2d4..39d946e0a47c 100644
--- a/arch/arm/boot/dts/at91-sam9x60ek.dts
+++ b/arch/arm/boot/dts/at91-sam9x60ek.dts
@@ -309,6 +309,10 @@
        };
 };
 
+&gpbr {
+       status = "okay";
+};
+
 &i2s {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_i2s_default>;
@@ -613,6 +617,11 @@
        };
 };
 
+&rtt {
+       atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
+       status = "okay";
+};
+
 &shutdown_controller {
        atmel,shdwc-debouncer = <976>;
        status = "okay";
diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi
index 6763423d64b8..d10843da4a85 100644
--- a/arch/arm/boot/dts/sam9x60.dtsi
+++ b/arch/arm/boot/dts/sam9x60.dtsi
@@ -661,6 +661,13 @@
                                status = "disabled";
                        };
 
+                       rtt: rtt@fffffe20 {
+                               compatible = "microchip,sam9x60-rtt", 
"atmel,at91sam9260-rtt";
+                               reg = <0xfffffe20 0x20>;
+                               interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                               clocks = <&clk32k 0>;
+                       };
+
                        pit: timer@fffffe40 {
                                compatible = "atmel,at91sam9260-pit";
                                reg = <0xfffffe40 0x10>;
-- 
2.7.4