The Cortex-A76 uses some implementation defined perf events. Per Cortex-A76 TRM r4p0, section C2.3 PMU Events (pages C2-386 to C2-394), we can reuse Cortex-A57's perf events mapping currently.
Signed-off-by: Jisheng Zhang <[email protected]> --- arch/arm64/kernel/perf_event.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 55e1d75af708..4fb13fbdc2df 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -1127,7 +1127,7 @@ static int armv8_a75_pmu_init(struct arm_pmu *cpu_pmu) static int armv8_a76_pmu_init(struct arm_pmu *cpu_pmu) { return armv8_pmu_init(cpu_pmu, "armv8_cortex_a76", - armv8_pmuv3_map_event, NULL, NULL); + armv8_a57_map_event, NULL, NULL); } static int armv8_a77_pmu_init(struct arm_pmu *cpu_pmu) -- 2.27.0
