This patch add spi-nand DT nodes to the applicable Sparx5 boards.
Signed-off-by: Lars Povlsen <[email protected]>
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 20 ++++++++++++++++
.../boot/dts/microchip/sparx5_pcb125.dts | 7 ++++++
.../boot/dts/microchip/sparx5_pcb134.dts | 22 ++++++++++++++++++
.../boot/dts/microchip/sparx5_pcb135.dts | 23 +++++++++++++++++++
4 files changed, 72 insertions(+)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 2404bcc08b89d..dd666d185e466 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -201,6 +201,26 @@ gpio: pinctrl@6110101e0 {
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
+ cs1_pins: cs1-pins {
+ pins = "GPIO_16";
+ function = "si";
+ };
+
+ cs2_pins: cs2-pins {
+ pins = "GPIO_17";
+ function = "si";
+ };
+
+ cs3_pins: cs3-pins {
+ pins = "GPIO_18";
+ function = "si";
+ };
+
+ si2_pins: si2-pins {
+ pins = "GPIO_39", "GPIO_40", "GPIO_41";
+ function = "si2";
+ };
+
uart_pins: uart-pins {
pins = "GPIO_10", "GPIO_11";
function = "uart";
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
index d8b5d23abfab0..94c4c3fd5a786 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
@@ -46,6 +46,13 @@ spi-flash@0 {
spi-max-frequency = <8000000>; /* input clock */
reg = <0>; /* CS0 */
};
+ spi-flash@1 {
+ compatible = "spi-nand";
+ pinctrl-0 = <&cs1_pins>;
+ pinctrl-names = "default";
+ spi-max-frequency = <8000000>;
+ reg = <1>; /* CS1 */
+ };
};
&i2c1 {
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts
b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts
index feee4e99ff57c..7aee0548e44cb 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts
@@ -15,3 +15,25 @@ memory@0 {
reg = <0x00000000 0x00000000 0x10000000>;
};
};
+
+&gpio {
+ cs14_pins: cs14-pins {
+ pins = "GPIO_44";
+ function = "si";
+ };
+};
+
+&spi0 {
+ pinctrl-0 = <&si2_pins>;
+ pinctrl-names = "default";
+ /* Dedicated SPI2 interface */
+ spi-flash@e {
+ compatible = "spi-nand";
+ pinctrl-0 = <&cs14_pins>;
+ pinctrl-names = "default";
+ spi-max-frequency = <42000000>;
+ reg = <14>;
+ microchip,spi-interface2; /* SPI2 */
+ snps,rx-sample-delay-ns = <7>; /* Tune for speed */
+ };
+};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts
b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts
index 20e409a9be196..8f2329ce02030 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts
@@ -15,3 +15,26 @@ memory@0 {
reg = <0x00000000 0x00000000 0x10000000>;
};
};
+
+&gpio {
+ cs14_pins: cs14-pins {
+ pins = "GPIO_44";
+ function = "si";
+ };
+};
+
+&spi0 {
+ status = "okay";
+ pinctrl-0 = <&si2_pins>;
+ pinctrl-names = "default";
+ /* Dedicated SPI2 interface */
+ spi-flash@e {
+ compatible = "spi-nand";
+ pinctrl-0 = <&cs14_pins>;
+ pinctrl-names = "default";
+ spi-max-frequency = <42000000>;
+ reg = <14>;
+ microchip,spi-interface2; /* SPI2 */
+ snps,rx-sample-delay-ns = <7>; /* Tune for speed */
+ };
+};
--
2.27.0
