On 16/06/20 09:33, Xiaoyao Li wrote:
> Only MSR address range 0x800 through 0x8ff is architecturally reserved
> and dedicated for accessing APIC registers in x2APIC mode.
>
> Fixes: 0105d1a52640 ("KVM: x2apic interface to lapic")
> Signed-off-by: Xiaoyao Li <[email protected]>
> ---
> arch/x86/kvm/x86.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> index 00c88c2f34e4..29d9b078ce69 100644
> --- a/arch/x86/kvm/x86.c
> +++ b/arch/x86/kvm/x86.c
> @@ -2856,7 +2856,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct
> msr_data *msr_info)
> return kvm_mtrr_set_msr(vcpu, msr, data);
> case MSR_IA32_APICBASE:
> return kvm_set_apic_base(vcpu, msr_info);
> - case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
> + case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
> return kvm_x2apic_msr_write(vcpu, msr, data);
> case MSR_IA32_TSCDEADLINE:
> kvm_set_lapic_tscdeadline_msr(vcpu, data);
> @@ -3196,7 +3196,7 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct
> msr_data *msr_info)
> case MSR_IA32_APICBASE:
> msr_info->data = kvm_get_apic_base(vcpu);
> break;
> - case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
> + case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
> return kvm_x2apic_msr_read(vcpu, msr_info->index,
> &msr_info->data);
> case MSR_IA32_TSCDEADLINE:
> msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
>
Queued, thanks (with Cc to stable).
Paolo
