On Tue 23 Jun 15:48 PDT 2020, Konrad Dybcio wrote:
> Add a proper CPU map to enable the use of all 8 cores.
>
> Signed-off-by: Konrad Dybcio <konradyb...@gmail.com>
Applied, thanks
> ---
> arch/arm64/boot/dts/qcom/msm8994.dtsi | 112 +++++++++++++++++++++++---
> 1 file changed, 102 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi
> b/arch/arm64/boot/dts/qcom/msm8994.dtsi
> index 23e50c30669b..e7f4b06eb12c 100644
> --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi
> @@ -28,24 +28,116 @@ sleep_clk: sleep_clk {
> };
>
> cpus {
> - #address-cells = <1>;
> + #address-cells = <2>;
> #size-cells = <0>;
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + L2_0: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + };
> + };
> +
> + CPU1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0 0x1>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + };
> +
> + CPU2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0 0x2>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + };
> +
> + CPU3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0 0x3>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + };
> +
> + CPU4: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x100>;
> + enable-method = "psci";
> + next-level-cache = <&L2_1>;
> + L2_1: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + };
> + };
> +
> + CPU5: cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x101>;
> + enable-method = "psci";
> + next-level-cache = <&L2_1>;
> + };
> +
> + CPU6: cpu@102 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x101>;
> + enable-method = "psci";
> + next-level-cache = <&L2_1>;
> + };
> +
> + CPU7: cpu@103 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57";
> + reg = <0x0 0x101>;
> + enable-method = "psci";
> + next-level-cache = <&L2_1>;
> + };
> +
> cpu-map {
> cluster0 {
> core0 {
> cpu = <&CPU0>;
> };
> +
> + core1 {
> + cpu = <&CPU1>;
> + };
> +
> + core2 {
> + cpu = <&CPU2>;
> + };
> +
> + core3 {
> + cpu = <&CPU3>;
> + };
> };
> - };
>
> - CPU0: cpu@0 {
> - device_type = "cpu";
> - compatible = "arm,cortex-a53";
> - reg = <0x0>;
> - next-level-cache = <&L2_0>;
> - L2_0: l2-cache {
> - compatible = "cache";
> - cache-level = <2>;
> + cluster1 {
> + core0 {
> + cpu = <&CPU4>;
> + };
> +
> + core1 {
> + cpu = <&CPU5>;
> + };
> +
> + core2 {
> + cpu = <&CPU6>;
> + };
> +
> + core3 {
> + cpu = <&CPU7>;
> + };
> };
> };
> };
> --
> 2.27.0
>
