add edma2 on i.mx8qxp.
Signed-off-by: Robin Gong <yibin.g...@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 38 ++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index e46faac..3f4fa59d 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -300,6 +300,44 @@
status = "disabled";
};
+ edma2: dma-controller@5a1f0000 {
+ compatible = "fsl,imx8qm-edma";
+ reg = <0x5a280000 0x10000>, /* channel8 UART0 rx */
+ <0x5a290000 0x10000>, /* channel9 UART0 tx */
+ <0x5a2a0000 0x10000>, /* channel10 UART1 rx */
+ <0x5a2b0000 0x10000>, /* channel11 UART1 tx */
+ <0x5a2c0000 0x10000>, /* channel12 UART2 rx */
+ <0x5a2d0000 0x10000>, /* channel13 UART2 tx */
+ <0x5a2e0000 0x10000>, /* channel14 UART3 rx */
+ <0x5a2f0000 0x10000>; /* channel15 UART3 tx */
+ #dma-cells = <3>;
+ dma-channels = <8>;
+ interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx",
+ "edma2-chan10-rx", "edma2-chan11-tx",
+ "edma2-chan12-rx", "edma2-chan13-tx",
+ "edma2-chan14-rx", "edma2-chan15-tx";
+ power-domains = <&pd IMX_SC_R_DMA_2_CH8>,
+ <&pd IMX_SC_R_DMA_2_CH9>,
+ <&pd IMX_SC_R_DMA_2_CH10>,
+ <&pd IMX_SC_R_DMA_2_CH11>,
+ <&pd IMX_SC_R_DMA_2_CH12>,
+ <&pd IMX_SC_R_DMA_2_CH13>,
+ <&pd IMX_SC_R_DMA_2_CH14>,
+ <&pd IMX_SC_R_DMA_2_CH15>;
+ power-domain-names = "edma2-chan8", "edma2-chan9",
+ "edma2-chan10", "edma2-chan11",
+ "edma2-chan12", "edma2-chan13",
+ "edma2-chan14", "edma2-chan15";
+ };
+
adma_i2c0: i2c@5a800000 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x5a800000 0x4000>;
--
2.7.4
