This patch add spi-nand DT nodes to the applicable Sparx5 boards.
Signed-off-by: Lars Povlsen <[email protected]>
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 20 ++++++++++++
.../arm64/boot/dts/microchip/sparx5_nand.dtsi | 32 +++++++++++++++++++
.../boot/dts/microchip/sparx5_pcb125.dts | 7 ++++
.../boot/dts/microchip/sparx5_pcb134.dts | 1 +
.../boot/dts/microchip/sparx5_pcb135.dts | 1 +
5 files changed, 61 insertions(+)
create mode 100644 arch/arm64/boot/dts/microchip/sparx5_nand.dtsi
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 2831935a489e1..21a85359d3492 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -210,6 +210,26 @@ gpio: pinctrl@6110101e0 {
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
+ cs1_pins: cs1-pins {
+ pins = "GPIO_16";
+ function = "si";
+ };
+
+ cs2_pins: cs2-pins {
+ pins = "GPIO_17";
+ function = "si";
+ };
+
+ cs3_pins: cs3-pins {
+ pins = "GPIO_18";
+ function = "si";
+ };
+
+ si2_pins: si2-pins {
+ pins = "GPIO_39", "GPIO_40", "GPIO_41";
+ function = "si2";
+ };
+
uart_pins: uart-pins {
pins = "GPIO_10", "GPIO_11";
function = "uart";
diff --git a/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi
b/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi
new file mode 100644
index 0000000000000..fd9523d9efbe3
--- /dev/null
+++ b/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ */
+
+&gpio {
+ cs14_pins: cs14-pins {
+ pins = "GPIO_44";
+ function = "si";
+ };
+};
+
+&mux {
+ /* CS14 (NAND) is on SPI2 */
+ mux@e {
+ reg = <14>;
+ microchip,bus-interface = <1>;
+ };
+};
+
+&spi0 {
+ pinctrl-0 = <&si2_pins>;
+ pinctrl-names = "default";
+ spi-flash@e {
+ compatible = "spi-nand";
+ pinctrl-0 = <&cs14_pins>;
+ pinctrl-names = "default";
+ spi-max-frequency = <42000000>;
+ reg = <14>;
+ snps,rx-sample-delay-ns = <7>; /* Tune for speed */
+ };
+};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
index d8b5d23abfab0..94c4c3fd5a786 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
@@ -46,6 +46,13 @@ spi-flash@0 {
spi-max-frequency = <8000000>; /* input clock */
reg = <0>; /* CS0 */
};
+ spi-flash@1 {
+ compatible = "spi-nand";
+ pinctrl-0 = <&cs1_pins>;
+ pinctrl-names = "default";
+ spi-max-frequency = <8000000>;
+ reg = <1>; /* CS1 */
+ };
};
&i2c1 {
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts
b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts
index feee4e99ff57c..45ca1af7e8500 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134.dts
@@ -5,6 +5,7 @@
/dts-v1/;
#include "sparx5_pcb134_board.dtsi"
+#include "sparx5_nand.dtsi"
/ {
model = "Sparx5 PCB134 Reference Board (NAND)";
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts
b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts
index 20e409a9be196..647cdb38b1130 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135.dts
@@ -5,6 +5,7 @@
/dts-v1/;
#include "sparx5_pcb135_board.dtsi"
+#include "sparx5_nand.dtsi"
/ {
model = "Sparx5 PCB135 Reference Board (NAND)";
--
2.27.0
