Re: [PATCH v7 7/7] arm64: dts: add dts nodes for MT6779

[Matthias Brugger]

On 02/07/2020 14:57, Hanks Chen wrote:

this adds initial MT6779 dts settings for board support,
including cpu, gic, timer, ccf, pinctrl, uart, sysirq...etc.

Signed-off-by: Hanks Chen <hanks.c...@mediatek.com>
---
  arch/arm64/boot/dts/mediatek/Makefile       |    1 +
  arch/arm64/boot/dts/mediatek/mt6779-evb.dts |   31 +++
  arch/arm64/boot/dts/mediatek/mt6779.dtsi    |  271 +++++++++++++++++++++++++++
  3 files changed, 303 insertions(+)
  create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts
  create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi

[...]

+
+               uart2: serial@11004000 {
+                       compatible = "mediatek,mt6779-uart",
+                                    "mediatek,mt6577-uart";
+                       reg = <0 0x11004000 0 0x400>;
+                       interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_LOW>;
+                       clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART1>;

I suppose that should be:

clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART2>;


Regards,
Matthias

+                       clock-names = "baud", "bus";
+                       status = "disabled";
+               };
+
+               audio: clock-controller@11210000 {
+                       compatible = "mediatek,mt6779-audio", "syscon";
+                       reg = <0 0x11210000 0 0x1000>;
+                       #clock-cells = <1>;
+               };
+
+               mfgcfg: clock-controller@13fbf000 {
+                       compatible = "mediatek,mt6779-mfgcfg", "syscon";
+                       reg = <0 0x13fbf000 0 0x1000>;
+                       #clock-cells = <1>;
+               };
+
+               mmsys: syscon@14000000 {
+                       compatible = "mediatek,mt6779-mmsys", "syscon";
+                       reg = <0 0x14000000 0 0x1000>;
+                       #clock-cells = <1>;
+               };
+
+               imgsys: clock-controller@15020000 {
+                       compatible = "mediatek,mt6779-imgsys", "syscon";
+                       reg = <0 0x15020000 0 0x1000>;
+                       #clock-cells = <1>;
+               };
+
+               vdecsys: clock-controller@16000000 {
+                       compatible = "mediatek,mt6779-vdecsys", "syscon";
+                       reg = <0 0x16000000 0 0x1000>;
+                       #clock-cells = <1>;
+               };
+
+               vencsys: clock-controller@17000000 {
+                       compatible = "mediatek,mt6779-vencsys", "syscon";
+                       reg = <0 0x17000000 0 0x1000>;
+                       #clock-cells = <1>;
+               };
+
+               camsys: clock-controller@1a000000 {
+                       compatible = "mediatek,mt6779-camsys", "syscon";
+                       reg = <0 0x1a000000 0 0x10000>;
+                       #clock-cells = <1>;
+               };
+
+               ipesys: clock-controller@1b000000 {
+                       compatible = "mediatek,mt6779-ipesys", "syscon";
+                       reg = <0 0x1b000000 0 0x1000>;
+                       #clock-cells = <1>;
+               };
+
+       };
+};