From: Bolarinwa Olayemi Saheed <[email protected]> On failure pcie_capability_read_dword() sets it's last parameter, val to 0. However, with Patch 14/14, it is possible that val is set to ~0 on failure. This would introduce a bug because (x & x) == (~0 & x).
This bug can be avoided if the return value of pcie_capability_read_dword is checked to confirm success. Check the return value of pcie_capability_read_dword() to ensure success. Suggested-by: Bjorn Helgaas <[email protected]> Signed-off-by: Bolarinwa Olayemi Saheed <[email protected]> --- drivers/pci/pcie/aspm.c | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index b17e5ffd31b1..32aa9d57672a 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -176,7 +176,7 @@ static void pcie_set_clkpm(struct pcie_link_state *link, int enable) static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) { - int capable = 1, enabled = 1; + int ret, capable = 1, enabled = 1; u32 reg32; u16 reg16; struct pci_dev *child; @@ -184,14 +184,14 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) /* All functions should have the same cap and state, take the worst */ list_for_each_entry(child, &linkbus->devices, bus_list) { - pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32); - if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) { + ret = pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32); + if (ret || !(reg32 & PCI_EXP_LNKCAP_CLKPM)) { capable = 0; enabled = 0; break; } - pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16); - if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN)) + ret = pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16); + if (ret || !(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN)) enabled = 0; } link->clkpm_enabled = enabled; @@ -205,6 +205,7 @@ static bool pcie_retrain_link(struct pcie_link_state *link) struct pci_dev *parent = link->pdev; unsigned long end_jiffies; u16 reg16; + int ret; pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); reg16 |= PCI_EXP_LNKCTL_RL; @@ -222,8 +223,8 @@ static bool pcie_retrain_link(struct pcie_link_state *link) /* Wait for link training end. Break out after waiting for timeout */ end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT; do { - pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); - if (!(reg16 & PCI_EXP_LNKSTA_LT)) + ret = pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); + if (ret || !(reg16 & PCI_EXP_LNKSTA_LT)) break; msleep(1); } while (time_before(jiffies, end_jiffies)); @@ -237,7 +238,7 @@ static bool pcie_retrain_link(struct pcie_link_state *link) */ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) { - int same_clock = 1; + int ret, same_clock = 1; u16 reg16, parent_reg, child_reg[8]; struct pci_dev *child, *parent = link->pdev; struct pci_bus *linkbus = parent->subordinate; @@ -249,24 +250,24 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) BUG_ON(!pci_is_pcie(child)); /* Check downstream component if bit Slot Clock Configuration is 1 */ - pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16); - if (!(reg16 & PCI_EXP_LNKSTA_SLC)) + ret = pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16); + if (ret || !(reg16 & PCI_EXP_LNKSTA_SLC)) same_clock = 0; /* Check upstream component if bit Slot Clock Configuration is 1 */ - pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); - if (!(reg16 & PCI_EXP_LNKSTA_SLC)) + ret = pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); + if (ret || !(reg16 & PCI_EXP_LNKSTA_SLC)) same_clock = 0; /* Port might be already in common clock mode */ - pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); - if (same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) { + ret = pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); + if (!ret && same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) { bool consistent = true; list_for_each_entry(child, &linkbus->devices, bus_list) { - pcie_capability_read_word(child, PCI_EXP_LNKCTL, + ret = pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16); - if (!(reg16 & PCI_EXP_LNKCTL_CCC)) { + if (ret || !(reg16 & PCI_EXP_LNKCTL_CCC)) { consistent = false; break; } -- 2.18.2
