Quoting Claudiu Beznea (2020-07-22 00:38:13)
> According to datasheet the range of 600-1200MHz is for the
> frequency generated by the fractional part of the PLL (namely
> Fcorepllck according to datasheet). With this in mind the output
> range of the PLL itself (fractional + div), taking into account
> that the divider is 8 bits wide, is 600/256-1200Hz=2.3-1200MHz.
>
> Fixes: a436c2a447e59 ("clk: at91: add sam9x60 PLL driver")
> Signed-off-by: Claudiu Beznea <[email protected]>
> ---
Applied to clk-next
