Quoting Claudiu Beznea (2020-07-22 00:38:24) > Some of the SAMA7G5 PLLs support multiple outputs (e.g. AUDIO PLL). > For these, split the PLL clock in two: fractional clock and > divider clock. In case PLLs supports multiple outputs (since these > outputs are dividers (with different settings) sharing the same > fractional part), it will register one fractional clock and multiple > divider clocks (dividers sharing the fractional clock). > > Signed-off-by: Claudiu Beznea <[email protected]> > ---
Applied to clk-next
