* Ricardo Neri <[email protected]> wrote:
> A recent submission to LKML introduced a CPU feature flag for a new > Intel architecture Serializing Instruction, SERIALIZE [1]. Unlike the > existing Serializing Instructions, this new instruction does not have > side effects such as clobbering registers or exiting to a hypervisor. > > As stated in the Intel "extensions" (ISE) manual [2], this instruction > will appear first in Sapphire Rapids and Alder Lake. > > Andy Lutomirski suggested to use this instruction in sync_core() as it > serves the very purpose of this function [3]. > > For completeness, I picked patch #3 from Cathy's series (and has become > patch #1 here) [1]. Her series depends on such patch to build correctly. > Maybe it can be merged independently while the discussion continues? > > Thanks and BR, > Ricardo > > [1]. > https://lore.kernel.org/kvm/[email protected]/ > [2]. > https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf > [3]. > https://lore.kernel.org/kvm/CALCETrWudiF8G8r57r5i4JefuP5biG1kHg==0o8yxb-bys-...@mail.gmail.com/ > > Ricardo Neri (4): > x86/cpufeatures: Add enumeration for SERIALIZE instruction > x86/cpu: Relocate sync_core() to sync_core.h > x86/cpu: Refactor sync_core() for readability > x86/cpu: Use SERIALIZE in sync_core() when available I've picked up the first 3 preparatory patches into tip:x86/cpu, as they are valid improvements even without the 4th patch. The actual functionality in the 4th patch still needs work. Thannks, Ingo
