From: Christian Eggers
> Sent: 28 July 2020 10:30
>
> SPI eeproms are addressed by byte.
They also support multi-byte writes - possibly with alignment
restrictions.
So forcing 4-byte writes (at aligned addresses) would typically
speed up writes by a factor of 4 over byte writes.
So does this fix a problem?
If so what.
So setting the 'stride' to 4 may be a compromise.
Looking at some code that writes the EPCQ for Altera FPGA
(which I think is just SPI) it does aligned 256 byte writes.
The long writes (and the 4-bit physical interface) are needed
to get the write times down to a sensible value.
David
>
> Signed-off-by: Christian Eggers <cegg...@arri.de>
> Cc: sta...@vger.kernel.org
> ---
> drivers/misc/eeprom/at25.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/misc/eeprom/at25.c b/drivers/misc/eeprom/at25.c
> index 0e7c8dc01195..4e57eb145fcc 100644
> --- a/drivers/misc/eeprom/at25.c
> +++ b/drivers/misc/eeprom/at25.c
> @@ -358,7 +358,7 @@ static int at25_probe(struct spi_device *spi)
> at25->nvmem_config.reg_read = at25_ee_read;
> at25->nvmem_config.reg_write = at25_ee_write;
> at25->nvmem_config.priv = at25;
> - at25->nvmem_config.stride = 4;
> + at25->nvmem_config.stride = 1;
> at25->nvmem_config.word_size = 1;
> at25->nvmem_config.size = chip.byte_len;
>
> --
> Christian Eggers
> Embedded software developer
>
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