Newer MTK chip support more than 8GB of dram. Replace support_33bits
with more general dma_max_support and remove mtk_i2c_set_4g_mode.

Signed-off-by: Qii Wang <qii.w...@mediatek.com>
---
 drivers/i2c/busses/i2c-mt65xx.c | 38 +++++++++++++++++---------------------
 1 file changed, 17 insertions(+), 21 deletions(-)

diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index e6b984a..49777a6 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -204,11 +204,11 @@ struct mtk_i2c_compatible {
        unsigned char dcm: 1;
        unsigned char auto_restart: 1;
        unsigned char aux_len_reg: 1;
-       unsigned char support_33bits: 1;
        unsigned char timing_adjust: 1;
        unsigned char dma_sync: 1;
        unsigned char ltiming_adjust: 1;
        unsigned char apdma_sync: 1;
+       unsigned char max_dma_support;
 };
 
 struct mtk_i2c_ac_timing {
@@ -311,11 +311,11 @@ struct i2c_spec_values {
        .dcm = 1,
        .auto_restart = 1,
        .aux_len_reg = 1,
-       .support_33bits = 1,
        .timing_adjust = 1,
        .dma_sync = 0,
        .ltiming_adjust = 0,
        .apdma_sync = 0,
+       .max_dma_support = 33,
 };
 
 static const struct mtk_i2c_compatible mt6577_compat = {
@@ -325,11 +325,11 @@ struct i2c_spec_values {
        .dcm = 1,
        .auto_restart = 0,
        .aux_len_reg = 0,
-       .support_33bits = 0,
        .timing_adjust = 0,
        .dma_sync = 0,
        .ltiming_adjust = 0,
        .apdma_sync = 0,
+       .max_dma_support = 32,
 };
 
 static const struct mtk_i2c_compatible mt6589_compat = {
@@ -339,11 +339,11 @@ struct i2c_spec_values {
        .dcm = 0,
        .auto_restart = 0,
        .aux_len_reg = 0,
-       .support_33bits = 0,
        .timing_adjust = 0,
        .dma_sync = 0,
        .ltiming_adjust = 0,
        .apdma_sync = 0,
+       .max_dma_support = 32,
 };
 
 static const struct mtk_i2c_compatible mt7622_compat = {
@@ -353,11 +353,11 @@ struct i2c_spec_values {
        .dcm = 1,
        .auto_restart = 1,
        .aux_len_reg = 1,
-       .support_33bits = 0,
        .timing_adjust = 0,
        .dma_sync = 0,
        .ltiming_adjust = 0,
        .apdma_sync = 0,
+       .max_dma_support = 32,
 };
 
 static const struct mtk_i2c_compatible mt8173_compat = {
@@ -366,11 +366,11 @@ struct i2c_spec_values {
        .dcm = 1,
        .auto_restart = 1,
        .aux_len_reg = 1,
-       .support_33bits = 1,
        .timing_adjust = 0,
        .dma_sync = 0,
        .ltiming_adjust = 0,
        .apdma_sync = 0,
+       .max_dma_support = 33,
 };
 
 static const struct mtk_i2c_compatible mt8183_compat = {
@@ -380,11 +380,11 @@ struct i2c_spec_values {
        .dcm = 0,
        .auto_restart = 1,
        .aux_len_reg = 1,
-       .support_33bits = 1,
        .timing_adjust = 1,
        .dma_sync = 1,
        .ltiming_adjust = 1,
        .apdma_sync = 0,
+       .max_dma_support = 33,
 };
 
 static const struct of_device_id mtk_i2c_of_match[] = {
@@ -796,11 +796,6 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned 
int parent_clk)
        return 0;
 }
 
-static inline u32 mtk_i2c_set_4g_mode(dma_addr_t addr)
-{
-       return (addr & BIT_ULL(32)) ? I2C_DMA_4G_MODE : I2C_DMA_CLR_FLAG;
-}
-
 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
                               int num, int left_num)
 {
@@ -885,8 +880,8 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct 
i2c_msg *msgs,
                        return -ENOMEM;
                }
 
-               if (i2c->dev_comp->support_33bits) {
-                       reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
+               if (i2c->dev_comp->max_dma_support > 32) {
+                       reg_4g_mode = upper_32_bits(rpaddr);
                        writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
                }
 
@@ -908,8 +903,8 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct 
i2c_msg *msgs,
                        return -ENOMEM;
                }
 
-               if (i2c->dev_comp->support_33bits) {
-                       reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
+               if (i2c->dev_comp->max_dma_support > 32) {
+                       reg_4g_mode = upper_32_bits(wpaddr);
                        writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
                }
 
@@ -954,11 +949,11 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, 
struct i2c_msg *msgs,
                        return -ENOMEM;
                }
 
-               if (i2c->dev_comp->support_33bits) {
-                       reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
+               if (i2c->dev_comp->max_dma_support > 32) {
+                       reg_4g_mode = upper_32_bits(wpaddr);
                        writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
 
-                       reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
+                       reg_4g_mode = upper_32_bits(rpaddr);
                        writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
                }
 
@@ -1232,8 +1227,9 @@ static int mtk_i2c_probe(struct platform_device *pdev)
                return -EINVAL;
        }
 
-       if (i2c->dev_comp->support_33bits) {
-               ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(33));
+       if (i2c->dev_comp->max_dma_support > 32) {
+               ret = dma_set_mask(&pdev->dev,
+                               DMA_BIT_MASK(i2c->dev_comp->max_dma_support));
                if (ret) {
                        dev_err(&pdev->dev, "dma_set_mask return error.\n");
                        return ret;
-- 
1.9.1

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