On Wed, Aug 12, 2020 at 02:30:38PM +0800, Wanpeng Li wrote:
> From: Wanpeng Li <wanpen...@tencent.com>
>
> Check apic_lvtt_tscdeadline() mode directly instead of apic_lvtt_oneshot()
> and apic_lvtt_period() to guarantee the timer is in tsc-deadline mode when
> wrmsr MSR_IA32_TSCDEADLINE.
>
> Signed-off-by: Wanpeng Li <wanpen...@tencent.com>
Gah, I take back my comment about squashing these, I assumed this was the
same fix but just in the write path.
Reviewed-by: Sean Christopherson <sean.j.christopher...@intel.com>
> ---
> v1 -> v2:
> * fix indentation
>
> arch/x86/kvm/lapic.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> index 79599af..abaf48e 100644
> --- a/arch/x86/kvm/lapic.c
> +++ b/arch/x86/kvm/lapic.c
> @@ -2193,8 +2193,7 @@ void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu
> *vcpu, u64 data)
> {
> struct kvm_lapic *apic = vcpu->arch.apic;
>
> - if (!kvm_apic_present(vcpu) || apic_lvtt_oneshot(apic) ||
> - apic_lvtt_period(apic))
> + if (!kvm_apic_present(vcpu) || !apic_lvtt_tscdeadline(apic))
> return;
>
> hrtimer_cancel(&apic->lapic_timer.timer);
> --
> 2.7.4
>
