On 29-07-20, 21:00, Sivaprakash Murugesan wrote:
> There were some problem in ipq8074 Gen2 PCIe phy init sequence.
>
> 1. Few register values were wrongly updated in the phy init sequence.
> 2. The register QSERDES_RX_SIGDET_CNTRL is a RX tuning parameter
> register which is added in serdes table causing the wrong register
> was getting updated.
> 3. Clocks and resets were not added in the phy init.
>
> Fix these to make Gen2 PCIe port on ipq8074 devices to work.
Applied to fixes, thanks
>
> Fixes: eef243d04b2b6 ("phy: qcom-qmp: Add support for IPQ8074")
>
no need of empty line here, have fixed it up while applying
--
~Vinod
