Add devicetree binding documentation for GPI DMA controller implemented on Qualcomm SoCs
Signed-off-by: Vinod Koul <vk...@kernel.org> --- .../devicetree/bindings/dma/qcom-gpi.yaml | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/qcom-gpi.yaml diff --git a/Documentation/devicetree/bindings/dma/qcom-gpi.yaml b/Documentation/devicetree/bindings/dma/qcom-gpi.yaml new file mode 100644 index 000000000000..c56d601ad2d6 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/qcom-gpi.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/gpi-dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies Inc GPI DMA controller + +description: | + QCOM GPI DMA controller provides DMA capabilities for + peripheral buses such as I2C, UART, and SPI. + +maintainers: + - Vinod Koul <vk...@kernel.org> + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + compatible: + enum: + - qcom,gpi-dma + + reg: + maxItems: 1 + + interrupts: + description: + Interrupt lines for each GPII instance + maxItems: 14 + + qcom,max-num-gpii: + description: + Maximum number of GPII instances available + maxItems: 1 + + "#dma-cells": + const: 1 + + qcom,gpii-mask: + description: + Bitmap of supported GPII instances for OS + maxItems: 1 + + qcom,ev-factor: + description: + Event ring transfer size compare to channel transfer ring. Event + ring length = ev-factor * transfer ring size + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - qcom,max-num-gpii + - qcom,gpii-mask + - qcom,ev-factor + - "#dma-cells" + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + gpi_dma0: dma@800000 { + #dma-cells = <5>; + compatible = "qcom,gpi-dma"; + reg = <0 0x00800000 0 0x60000>; + qcom,max-num-gpii = <13>; + qcom,gpii-mask = <0xfa>; + qcom,ev-factor = <2>; + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; + }; + +... -- 2.26.2
