Add clock entry 130 for VSPR module, so that this module can be used on R8A7742 (RZ/G1H) SoC.
Note: The entry for VSPR clock was accidentally dropped from RZ/G manual when all the information related to RT were removed. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Biju Das <[email protected]> --- Similar details can be seen in commit 79ea9934b8df ("ARM: shmobile: r8a7790: Rename VSP1_(SY|RT) clocks to VSP1_(S|R)") for R-Car H2 --- drivers/clk/renesas/r8a7742-cpg-mssr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/renesas/r8a7742-cpg-mssr.c b/drivers/clk/renesas/r8a7742-cpg-mssr.c index e919828668a4..28b24c4e9d7d 100644 --- a/drivers/clk/renesas/r8a7742-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7742-cpg-mssr.c @@ -97,6 +97,7 @@ static const struct mssr_mod_clk r8a7742_mod_clks[] __initconst = { DEF_MOD("tmu0", 125, R8A7742_CLK_CP), DEF_MOD("vsp1du1", 127, R8A7742_CLK_ZS), DEF_MOD("vsp1du0", 128, R8A7742_CLK_ZS), + DEF_MOD("vspr", 130, R8A7742_CLK_ZS), DEF_MOD("vsp1-sy", 131, R8A7742_CLK_ZS), DEF_MOD("scifa2", 202, R8A7742_CLK_MP), DEF_MOD("scifa1", 203, R8A7742_CLK_MP), -- 2.17.1
