Transmit data pins will output zero when slots are masked or channels
are disabled. In CHMOD TDM mode, transmit data pins are tri-stated when
slots are masked or channels are disabled. When data pins are tri-stated,
there is noise on some channels when FS clock value is high and data is
read while fsclk is transitioning from high to low.

Signed-off-by: Cosmin-Gabriel Samoila <[email protected]>
Signed-off-by: Shengjiu Wang <[email protected]>
---
 sound/soc/fsl/fsl_sai.c | 12 ++++++++++--
 sound/soc/fsl/fsl_sai.h |  2 ++
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 62c5fdb678fc..33b194a5c1dc 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -486,6 +486,12 @@ static int fsl_sai_hw_params(struct snd_pcm_substream 
*substream,
 
        val_cr4 |= FSL_SAI_CR4_FRSZ(slots);
 
+       /* Output Mode - data pins transmit 0 when slots are masked
+        * or channels are disabled
+        */
+       if (tx)
+               val_cr4 |= FSL_SAI_CR4_CHMOD;
+
        /*
         * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
         * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
@@ -494,7 +500,8 @@ static int fsl_sai_hw_params(struct snd_pcm_substream 
*substream,
 
        if (!sai->is_slave_mode && fsl_sai_dir_is_synced(sai, adir)) {
                regmap_update_bits(sai->regmap, FSL_SAI_xCR4(!tx, ofs),
-                                  FSL_SAI_CR4_SYWD_MASK | 
FSL_SAI_CR4_FRSZ_MASK,
+                                  FSL_SAI_CR4_SYWD_MASK | 
FSL_SAI_CR4_FRSZ_MASK |
+                                  FSL_SAI_CR4_CHMOD_MASK,
                                   val_cr4);
                regmap_update_bits(sai->regmap, FSL_SAI_xCR5(!tx, ofs),
                                   FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
@@ -502,7 +509,8 @@ static int fsl_sai_hw_params(struct snd_pcm_substream 
*substream,
        }
 
        regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
-                          FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
+                          FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK |
+                          FSL_SAI_CR4_CHMOD_MASK,
                           val_cr4);
        regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs),
                           FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
index 6aba7d28f5f3..19cd4e1bbff9 100644
--- a/sound/soc/fsl/fsl_sai.h
+++ b/sound/soc/fsl/fsl_sai.h
@@ -119,6 +119,8 @@
 #define FSL_SAI_CR4_FRSZ_MASK  (0x1f << 16)
 #define FSL_SAI_CR4_SYWD(x)    (((x) - 1) << 8)
 #define FSL_SAI_CR4_SYWD_MASK  (0x1f << 8)
+#define FSL_SAI_CR4_CHMOD       BIT(5)
+#define FSL_SAI_CR4_CHMOD_MASK  BIT(5)
 #define FSL_SAI_CR4_MF         BIT(4)
 #define FSL_SAI_CR4_FSE                BIT(3)
 #define FSL_SAI_CR4_FSP                BIT(1)
-- 
2.27.0

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