On Tue, Sep 1, 2020 at 3:10 PM Kim Phillips <kim.phill...@amd.com> wrote: > > Later revisions of PPRs that post-date the original Family 17h events > submission patch add these events. > > Specifically, they were not in this 2017 revision of the F17h PPR: > > Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision > B1 Processors Rev 1.14 - April 15, 2017 > > But e.g., are included in this 2019 version of the PPR: > > Processor Programming Reference (PPR) for AMD Family 17h Model 18h, Revision > B1 Processors Rev. 3.14 - Sep 26, 2019 > > Signed-off-by: Kim Phillips <kim.phill...@amd.com>
Reviewed-by: Ian Rogers <irog...@google.com> Sanity checked manual and ran tests. Thanks, Ian > Fixes: 98c07a8f74f8 ("perf vendor events amd: perf PMU events for AMD Family > 17h") > Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 > Cc: Peter Zijlstra <pet...@infradead.org> > Cc: Ingo Molnar <mi...@redhat.com> > Cc: Arnaldo Carvalho de Melo <a...@kernel.org> > Cc: Mark Rutland <mark.rutl...@arm.com> > Cc: Alexander Shishkin <alexander.shish...@linux.intel.com> > Cc: Jiri Olsa <jo...@redhat.com> > Cc: Namhyung Kim <namhy...@kernel.org> > Cc: Vijay Thakkar <vijaythak...@me.com> > Cc: Andi Kleen <a...@linux.intel.com> > Cc: John Garry <john.ga...@huawei.com> > Cc: Kan Liang <kan.li...@linux.intel.com> > Cc: Yunfeng Ye <yeyunf...@huawei.com> > Cc: Jin Yao <yao....@linux.intel.com> > Cc: "Martin Liška" <mli...@suse.cz> > Cc: Borislav Petkov <b...@suse.de> > Cc: Jon Grimm <jon.gr...@amd.com> > Cc: Martin Jambor <mjam...@suse.cz> > Cc: Michael Petlan <mpet...@redhat.com> > Cc: William Cohen <wco...@redhat.com> > Cc: Stephane Eranian <eran...@google.com> > Cc: Ian Rogers <irog...@google.com> > Cc: linux-perf-us...@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > Cc: sta...@vger.kernel.org > --- > .../pmu-events/arch/x86/amdzen1/cache.json | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/tools/perf/pmu-events/arch/x86/amdzen1/cache.json > b/tools/perf/pmu-events/arch/x86/amdzen1/cache.json > index 404d4c569c01..695ed3ffa3a6 100644 > --- a/tools/perf/pmu-events/arch/x86/amdzen1/cache.json > +++ b/tools/perf/pmu-events/arch/x86/amdzen1/cache.json > @@ -249,6 +249,24 @@ > "BriefDescription": "Cycles with fill pending from L2. Total cycles > spent with one or more fill requests in flight from L2.", > "UMask": "0x1" > }, > + { > + "EventName": "l2_pf_hit_l2", > + "EventCode": "0x70", > + "BriefDescription": "L2 prefetch hit in L2.", > + "UMask": "0xff" > + }, > + { > + "EventName": "l2_pf_miss_l2_hit_l3", > + "EventCode": "0x71", > + "BriefDescription": "L2 prefetcher hits in L3. Counts all L2 prefetches > accepted by the L2 pipeline which miss the L2 cache and hit the L3.", > + "UMask": "0xff" > + }, > + { > + "EventName": "l2_pf_miss_l2_l3", > + "EventCode": "0x72", > + "BriefDescription": "L2 prefetcher misses in L3. All L2 prefetches > accepted by the L2 pipeline which miss the L2 and the L3 caches.", > + "UMask": "0xff" > + }, > { > "EventName": "l3_request_g1.caching_l3_cache_accesses", > "EventCode": "0x01", > -- > 2.27.0 >