Em Tue, Sep 01, 2020 at 05:09:41PM -0500, Kim Phillips escreveu: > Later revisions of PPRs that post-date the original Family 17h events > submission patch add these events. > > Specifically, they were not in this 2017 revision of the F17h PPR: > > Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision > B1 Processors Rev 1.14 - April 15, 2017 > > But e.g., are included in this 2019 version of the PPR: > > Processor Programming Reference (PPR) for AMD Family 17h Model 18h, Revision > B1 Processors Rev. 3.14 - Sep 26, 2019
Thanks, applied. - Arnaldo > Signed-off-by: Kim Phillips <[email protected]> > Fixes: 98c07a8f74f8 ("perf vendor events amd: perf PMU events for AMD Family > 17h") > Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 > Cc: Peter Zijlstra <[email protected]> > Cc: Ingo Molnar <[email protected]> > Cc: Arnaldo Carvalho de Melo <[email protected]> > Cc: Mark Rutland <[email protected]> > Cc: Alexander Shishkin <[email protected]> > Cc: Jiri Olsa <[email protected]> > Cc: Namhyung Kim <[email protected]> > Cc: Vijay Thakkar <[email protected]> > Cc: Andi Kleen <[email protected]> > Cc: John Garry <[email protected]> > Cc: Kan Liang <[email protected]> > Cc: Yunfeng Ye <[email protected]> > Cc: Jin Yao <[email protected]> > Cc: "Martin Liška" <[email protected]> > Cc: Borislav Petkov <[email protected]> > Cc: Jon Grimm <[email protected]> > Cc: Martin Jambor <[email protected]> > Cc: Michael Petlan <[email protected]> > Cc: William Cohen <[email protected]> > Cc: Stephane Eranian <[email protected]> > Cc: Ian Rogers <[email protected]> > Cc: [email protected] > Cc: [email protected] > Cc: [email protected] > --- > .../pmu-events/arch/x86/amdzen1/cache.json | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/tools/perf/pmu-events/arch/x86/amdzen1/cache.json > b/tools/perf/pmu-events/arch/x86/amdzen1/cache.json > index 404d4c569c01..695ed3ffa3a6 100644 > --- a/tools/perf/pmu-events/arch/x86/amdzen1/cache.json > +++ b/tools/perf/pmu-events/arch/x86/amdzen1/cache.json > @@ -249,6 +249,24 @@ > "BriefDescription": "Cycles with fill pending from L2. Total cycles > spent with one or more fill requests in flight from L2.", > "UMask": "0x1" > }, > + { > + "EventName": "l2_pf_hit_l2", > + "EventCode": "0x70", > + "BriefDescription": "L2 prefetch hit in L2.", > + "UMask": "0xff" > + }, > + { > + "EventName": "l2_pf_miss_l2_hit_l3", > + "EventCode": "0x71", > + "BriefDescription": "L2 prefetcher hits in L3. Counts all L2 prefetches > accepted by the L2 pipeline which miss the L2 cache and hit the L3.", > + "UMask": "0xff" > + }, > + { > + "EventName": "l2_pf_miss_l2_l3", > + "EventCode": "0x72", > + "BriefDescription": "L2 prefetcher misses in L3. All L2 prefetches > accepted by the L2 pipeline which miss the L2 and the L3 caches.", > + "UMask": "0xff" > + }, > { > "EventName": "l3_request_g1.caching_l3_cache_accesses", > "EventCode": "0x01", > -- > 2.27.0 > -- - Arnaldo
