On 17:52-20200907, Roger Quadros wrote:
> The SERDES lane control mux registers are present in the
> CTRLMMR space.
>
> Signed-off-by: Roger Quadros <rog...@ti.com>
> ---
> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> index 1702ac0bbf40..e72c7a0ccad5 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> @@ -18,6 +18,21 @@
> };
> };
>
> + scm_conf: scm-conf@100000 {
> + compatible = "ti,j721e-system-controller", "syscon",
> "simple-mfd";
> + reg = <0 0x00100000 0 0x1c000>;
Just to stay consistent with j7200 stuff we are trying to keep clean:
reg = <0x00 0x00100000 0x00 0x1c000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x00100000 0x1c000>;
ranges = <0x00 0x00 0x00100000 0x1c000>;
> +
> + serdes_ln_ctrl: serdes-ln-ctrl@4080 {
> + compatible = "mmio-mux";
> + #mux-control-cells = <1>;
> + mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0
> lane0/1 select */
> + <0x4088 0x3>, <0x408c 0x3>; /* SERDES0
> lane2/3 select */
> + };
> + };
> +
> gic500: interrupt-controller@1800000 {
> compatible = "arm,gic-v3";
> #address-cells = <2>;
> --
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>
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5
849D 1736 249D
