Do a bit of cleaning, to make the next patch looks more clear. The
details are as follows:
1. Remove a mismatched comment. It just temporarily disable a timer,
and the timer will be set to periodic mode later.
2. Add two local variables: timer1_base and timer2_base in
sp804_of_init(), To avoid repeatedly calculate the base address of
timer2, and make it easier to recognize timer1.
3. Delete the leading "__" of __sp804_clocksource_and_sched_clock_init()
and __sp804_clockevents_init().
No functional change.
Signed-off-by: Zhen Lei <thunder.leiz...@huawei.com>
---
drivers/clocksource/timer-sp804.c | 36 ++++++++++++++++++-------------
1 file changed, 21 insertions(+), 15 deletions(-)
diff --git a/drivers/clocksource/timer-sp804.c
b/drivers/clocksource/timer-sp804.c
index 97b41a493253..e0c3779621eb 100644
--- a/drivers/clocksource/timer-sp804.c
+++ b/drivers/clocksource/timer-sp804.c
@@ -65,10 +65,10 @@ static u64 notrace sp804_read(void)
return ~readl_relaxed(sched_clock_base + TIMER_VALUE);
}
-int __init __sp804_clocksource_and_sched_clock_init(void __iomem *base,
- const char *name,
- struct clk *clk,
- int use_sched_clock)
+int __init sp804_clocksource_and_sched_clock_init(void __iomem *base,
+ const char *name,
+ struct clk *clk,
+ int use_sched_clock)
{
long rate;
@@ -76,7 +76,6 @@ int __init __sp804_clocksource_and_sched_clock_init(void
__iomem *base,
if (rate < 0)
return -EINVAL;
- /* setup timer 0 as free-running clocksource */
writel(0, base + TIMER_CTRL);
writel(0xffffffff, base + TIMER_LOAD);
writel(0xffffffff, base + TIMER_VALUE);
@@ -159,7 +158,8 @@ static struct clock_event_device sp804_clockevent = {
.rating = 300,
};
-int __init __sp804_clockevents_init(void __iomem *base, unsigned int irq,
struct clk *clk, const char *name)
+int __init sp804_clockevents_init(void __iomem *base, unsigned int irq,
+ struct clk *clk, const char *name)
{
struct clock_event_device *evt = &sp804_clockevent;
long rate;
@@ -188,6 +188,8 @@ static int __init sp804_of_init(struct device_node *np)
{
static bool initialized = false;
void __iomem *base;
+ void __iomem *timer1_base;
+ void __iomem *timer2_base;
int irq, ret = -EINVAL;
u32 irq_num = 0;
struct clk *clk1, *clk2;
@@ -197,9 +199,12 @@ static int __init sp804_of_init(struct device_node *np)
if (!base)
return -ENXIO;
+ timer1_base = base;
+ timer2_base = base + TIMER_2_BASE;
+
/* Ensure timers are disabled */
- writel(0, base + TIMER_CTRL);
- writel(0, base + TIMER_2_BASE + TIMER_CTRL);
+ writel(0, timer1_base + TIMER_CTRL);
+ writel(0, timer2_base + TIMER_CTRL);
if (initialized || !of_device_is_available(np)) {
ret = -EINVAL;
@@ -228,21 +233,22 @@ static int __init sp804_of_init(struct device_node *np)
of_property_read_u32(np, "arm,sp804-has-irq", &irq_num);
if (irq_num == 2) {
- ret = __sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2,
name);
+ ret = sp804_clockevents_init(timer2_base, irq, clk2, name);
if (ret)
goto err;
- ret = __sp804_clocksource_and_sched_clock_init(base, name,
clk1, 1);
+ ret = sp804_clocksource_and_sched_clock_init(timer1_base,
+ name, clk1, 1);
if (ret)
goto err;
} else {
- ret = __sp804_clockevents_init(base, irq, clk1 , name);
+ ret = sp804_clockevents_init(timer1_base, irq, clk1, name);
if (ret)
goto err;
- ret =__sp804_clocksource_and_sched_clock_init(base +
TIMER_2_BASE,
- name, clk2, 1);
+ ret = sp804_clocksource_and_sched_clock_init(timer2_base,
+ name, clk2, 1);
if (ret)
goto err;
}
@@ -282,7 +288,7 @@ static int __init integrator_cp_of_init(struct device_node
*np)
goto err;
if (!init_count) {
- ret = __sp804_clocksource_and_sched_clock_init(base, name, clk,
0);
+ ret = sp804_clocksource_and_sched_clock_init(base, name, clk,
0);
if (ret)
goto err;
} else {
@@ -290,7 +296,7 @@ static int __init integrator_cp_of_init(struct device_node
*np)
if (irq <= 0)
goto err;
- ret = __sp804_clockevents_init(base, irq, clk, name);
+ ret = sp804_clockevents_init(base, irq, clk, name);
if (ret)
goto err;
}
--
2.26.0.106.g9fadedd
