This patch enables direct mappings over 32bit range to spi-mtk-nor.

Signed-off-by: Ikjoon Jang <i...@chromium.org>

---

 drivers/spi/spi-mtk-nor.c | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-mtk-nor.c b/drivers/spi/spi-mtk-nor.c
index 6e6ca2b8e6c8..eb93ae34e670 100644
--- a/drivers/spi/spi-mtk-nor.c
+++ b/drivers/spi/spi-mtk-nor.c
@@ -78,6 +78,8 @@
 #define MTK_NOR_REG_DMA_FADR           0x71c
 #define MTK_NOR_REG_DMA_DADR           0x720
 #define MTK_NOR_REG_DMA_END_DADR       0x724
+#define MTK_NOR_REG_DMA_DADR_HB                0x738
+#define MTK_NOR_REG_DMA_END_DADR_HB    0x73c
 
 #define MTK_NOR_PRG_MAX_SIZE           6
 // Reading DMA src/dst addresses have to be 16-byte aligned
@@ -101,6 +103,7 @@ struct mtk_nor {
        unsigned int spi_freq;
        bool wbuf_en;
        bool has_irq;
+       bool high_dma;
        struct completion op_done;
 };
 
@@ -279,6 +282,11 @@ static int mtk_nor_read_dma(struct mtk_nor *sp, u32 from, 
unsigned int length,
        writel(dma_addr, sp->base + MTK_NOR_REG_DMA_DADR);
        writel(dma_addr + length, sp->base + MTK_NOR_REG_DMA_END_DADR);
 
+       if (sp->high_dma) {
+               writel(dma_addr >> 32, sp->base + MTK_NOR_REG_DMA_DADR_HB);
+               writel((dma_addr + length) >> 32, sp->base + 
MTK_NOR_REG_DMA_END_DADR_HB);
+       }
+
        if (sp->has_irq) {
                reinit_completion(&sp->op_done);
                mtk_nor_rmw(sp, MTK_NOR_REG_IRQ_EN, MTK_NOR_IRQ_DMA, 0);
@@ -578,7 +586,8 @@ static const struct spi_controller_mem_ops mtk_nor_mem_ops 
= {
 };
 
 static const struct of_device_id mtk_nor_match[] = {
-       { .compatible = "mediatek,mt8173-nor" },
+       { .compatible = "mediatek,mt8192-nor", .data = (void *)36 },
+       { .compatible = "mediatek,mt8173-nor", .data = (void *)32 },
        { /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, mtk_nor_match);
@@ -591,6 +600,7 @@ static int mtk_nor_probe(struct platform_device *pdev)
        u8 *buffer;
        struct clk *spi_clk, *ctlr_clk;
        int ret, irq;
+       unsigned long dma_bits;
 
        base = devm_platform_ioremap_resource(pdev, 0);
        if (IS_ERR(base))
@@ -614,6 +624,12 @@ static int mtk_nor_probe(struct platform_device *pdev)
                buffer = (u8 *)(((ulong)buffer + MTK_NOR_DMA_ALIGN) &
                                ~MTK_NOR_DMA_ALIGN_MASK);
 
+       dma_bits = (unsigned long)of_device_get_match_data(&pdev->dev);
+       if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits))) {
+               dev_err(&pdev->dev, "failed to set dma mask(%lu)\n", dma_bits);
+               return -EINVAL;
+       }
+
        ctlr = spi_alloc_master(&pdev->dev, sizeof(*sp));
        if (!ctlr) {
                dev_err(&pdev->dev, "failed to allocate spi controller\n");
@@ -640,6 +656,7 @@ static int mtk_nor_probe(struct platform_device *pdev)
        sp->dev = &pdev->dev;
        sp->spi_clk = spi_clk;
        sp->ctlr_clk = ctlr_clk;
+       sp->high_dma = (dma_bits > 32);
 
        irq = platform_get_irq_optional(pdev, 0);
        if (irq < 0) {
-- 
2.28.0.526.ge36021eeef-goog

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