Fix bugs when detecting L2 cache sets value and ways value.
Signed-off-by: 周琰杰 (Zhou Yanjie) <[email protected]>
---
arch/mips/mm/sc-mips.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 97dc0511e63f..145b39ecb246 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -235,6 +235,7 @@ static inline int __init mips_sc_probe(void)
* According to config2 it would be 5-ways and 512-sets,
* but that is contradicted by all documentation.
*/
+ case MACH_INGENIC_X1000E:
case MACH_INGENIC_X1000:
c->scache.sets = 256;
c->scache.ways = 4;
--
2.11.0
