On 18/09/20 09:56, Borislav Petkov wrote: > On Thu, Sep 17, 2020 at 09:20:38PM +0000, Krish Sadhukhan wrote: >> In some hardware implementations, coherency between the encrypted and >> unencrypted mappings of the same physical page in a VM is enforced. In such a >> system, it is not required for software to flush the VM's page from all CPU >> caches in the system prior to changing the value of the C-bit for the page. >> >> Signed-off-by: Krish Sadhukhan <[email protected]> >> --- >> arch/x86/kvm/svm/sev.c | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c >> index 7bf7bf734979..3c9a45efdd4d 100644 >> --- a/arch/x86/kvm/svm/sev.c >> +++ b/arch/x86/kvm/svm/sev.c >> @@ -384,7 +384,8 @@ static void sev_clflush_pages(struct page *pages[], >> unsigned long npages) >> uint8_t *page_virtual; >> unsigned long i; >> >> - if (npages == 0 || pages == NULL) >> + if (this_cpu_has(X86_FEATURE_SME_COHERENT) || npages == 0 || >> + pages == NULL) >> return; >> >> for (i = 0; i < npages; i++) { >> -- > > Took the first two, Paolo lemme know if I should route this one through > tip too. > > Thx. >
Yeah, it's innocuous enough as far as conflicts are concerned. Acked-by: Paolo Bonzini <[email protected]> Paolo
