The ARMv8.3-SPE extension adds some new bits to the event packet fields. Handle bits 11 (alignment), 17 and 18 (SVE predication) when decoding the SPE buffer content.
Signed-off-by: Andre Przywara <[email protected]> --- .../util/arm-spe-decoder/arm-spe-pkt-decoder.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c index b94001b756c7..e633bb5b8e65 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c +++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c @@ -346,6 +346,23 @@ int arm_spe_pkt_desc(const struct arm_spe_pkt *packet, char *buf, buf += ret; blen -= ret; } + if (payload & BIT(11)) { + ret = snprintf(buf, buf_len, " ALIGNMENT"); + buf += ret; + blen -= ret; + } + } + if (idx > 2) { + if (payload & BIT(17)) { + ret = snprintf(buf, buf_len, " SVE-PARTIAL-PRED"); + buf += ret; + blen -= ret; + } + if (payload & BIT(18)) { + ret = snprintf(buf, buf_len, " SVE-EMPTY-PRED"); + buf += ret; + blen -= ret; + } } if (ret < 0) return ret; -- 2.17.1
