From: MingWang Li <[email protected]> When testing the ARMv8.2-TTS2UXN feature, setting bits of XN is unavailable. Because the control bit CTR_EL0.DIC is set by default on system.
But when CTR_EL0.DIC is set, software does not need to flush icache actively, instead of clearing XN bits.The patch, the commit id of which is 6ae4b6e0578886eb36cedbf99f04031d93f9e315, has implemented the function of CTR_EL0.DIC. Signed-off-by: MingWang Li <[email protected]> Signed-off-by: Henglong Fan <[email protected]> --- arch/arm64/include/asm/pgtable-prot.h | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h index 4d867c6446c4..5feb94882bf7 100644 --- a/arch/arm64/include/asm/pgtable-prot.h +++ b/arch/arm64/include/asm/pgtable-prot.h @@ -79,17 +79,7 @@ extern bool arm64_use_ng_mappings; __val; \ }) -#define PAGE_S2_XN \ - ({ \ - u64 __val; \ - if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC)) \ - __val = 0; \ - else \ - __val = PTE_S2_XN; \ - __val; \ - }) - -#define PAGE_S2 __pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(NORMAL) | PTE_S2_RDONLY | PAGE_S2_XN) +#define PAGE_S2 __pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(NORMAL) | PTE_S2_RDONLY | PTE_S2_XN) #define PAGE_S2_DEVICE __pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_S2_XN) #define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN) -- 2.19.1
