Add CSI-2 nodes to R8A779A0 R-Car V3U SoC.
Signed-off-by: Jacopo Mondi <[email protected]>
---
The chip manual reports that the CSI-2 units are fed with S1D1 and S1D2
clocks. The same applies to other SoCs, but none lists the two
additional clocks in the DTS node. So I left them out here as well.
---
arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 41 +++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
index 6cf77ce9aa93..83962ad30a1d 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
@@ -105,6 +105,47 @@ scif0: serial@e6e60000 {
status = "disabled";
};
+ csi40: csi2@feaa0000 {
+ compatible = "renesas,r8a779a0-csi2";
+ reg = <0 0xfeaa0000 0 0x10000>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 331>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 331>;
+ status = "disabled";
+ };
+
+ csi41: csi2@feab0000 {
+ compatible = "renesas,r8a779a0-csi2";
+ reg = <0 0xfeab0000 0 0x10000>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 400>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 400>;
+ status = "disabled";
+ };
+
+ csi42: csi2@fed60000 {
+ compatible = "renesas,r8a779a0-csi2";
+ reg = <0 0xfed60000 0 0x10000>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 401>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 401>;
+ status = "disabled";
+
+ };
+
+ csi43: csi2@fed70000 {
+ compatible = "renesas,r8a779a0-csi2";
+ reg = <0 0xfed70000 0 0x10000>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 402>;
+ power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
+ resets = <&cpg 402>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@f1000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
--
2.28.0
