Hi Andy.
> -----Original Message-----
> From: Andy Shevchenko <[email protected]>
> Sent: Thursday, November 12, 2020 10:29 PM
> To: Wan Mohamad, Wan Ahmad Zainie
> <[email protected]>
> Cc: [email protected]; [email protected]; [email protected]; linux-
> [email protected]; [email protected];
> [email protected]; Raja Subramanian, Lakshmi Bai
> <[email protected]>
> Subject: Re: [PATCH v3 2/2] phy: intel: Add Keem Bay USB PHY support
>
> On Thu, Nov 12, 2020 at 05:58:21PM +0800, Wan Ahmad Zainie wrote:
> > Add support for USB PHY on Intel Keem Bay SoC.
>
> Any elaboration here? What is this PHY (USB2 or USB3 or?.. etc)?
Yes, I can elaborate this.
>
> ...
>
> > +config PHY_INTEL_KEEMBAY_USB
> > + tristate "Intel Keem Bay USB PHY driver"
>
> > + depends on ARCH_KEEMBAY || (ARM64 && COMPILE_TEST)
>
> It seems other drivers that are not using ARM specific calls moved to
>
> depends on ARCH_KEEMBAY || COMPILE_TEST
I will fix in v4.
>
> > + depends on HAS_IOMEM
> > + select GENERIC_PHY
> > + select REGMAP_MMIO
>
> ...
>
> > +#define USS_CPR_MASK 0x7f
>
> GENMASK() ?
I will fix in v4.
>
> ...
>
> > +static const struct regmap_config keembay_regmap_config = {
> > + .reg_bits = 32,
> > + .val_bits = 32,
> > + .reg_stride = 4,
>
> .max_register?
It is optional. But yes, I can add,
.max_register = USS_USB_TIEOFFS_CONSTANTS_REG1
>
> > +};
>
> --
> With Best Regards,
> Andy Shevchenko
>
Best regards,
Zainie
