On Thu, 28 Jan 2021, at 04:53, Konstantin Aladyshev wrote: > AMD EthanolX CRB uses 2-byte POST codes which are sent to ports 0x80/0x81. > Currently ASPEED controller snoops only 0x80 port and therefore captures > only the lower byte of each POST code. > Enable secondary LPC snooping address to capture the higher byte of POST > codes. > > Signed-off-by: Konstantin Aladyshev <[email protected]> Reviewed-by: Andrew Jeffery <[email protected]>
- [PATCH] ARM: dts: aspeed: amd-ethanolx: Enable second... Konstantin Aladyshev
- Re: [PATCH] ARM: dts: aspeed: amd-ethanolx: Enab... Andrew Jeffery
