[PATCH 1/1] pinctrl: pinctrl-microchip-sgpio: Fix wrong register offset for IRQ trigger

[Lars Povlsen]

This patch fixes using a wrong register offset when configuring an IRQ
trigger type.

Fixes: be2dc859abd4 ("pinctrl: pinctrl-microchip-sgpio: Add irq support (for 
sparx5)")
Reported-by: Gustavo A. R. Silva <gustavo...@kernel.org>
Signed-off-by: Lars Povlsen <lars.povl...@microchip.com>
---
 drivers/pinctrl/pinctrl-microchip-sgpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/pinctrl-microchip-sgpio.c 
b/drivers/pinctrl/pinctrl-microchip-sgpio.c
index 6a43edefa490..61ba245bd0f8 100644
--- a/drivers/pinctrl/pinctrl-microchip-sgpio.c
+++ b/drivers/pinctrl/pinctrl-microchip-sgpio.c
@@ -574,7 +574,7 @@ static void microchip_sgpio_irq_settype(struct irq_data 
*data,
        /* Type value spread over 2 registers sets: low, high bit */
        sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, addr.bit,
                         BIT(addr.port), (!!(type & 0x1)) << addr.port);
-       sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER + SGPIO_MAX_BITS, addr.bit,
+       sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, SGPIO_MAX_BITS + addr.bit,
                         BIT(addr.port), (!!(type & 0x2)) << addr.port);

        if (type == SGPIO_INT_TRG_LEVEL)
--
2.25.1