Hi Gustavo, I love your patch! Perhaps something to improve:
[auto build test WARNING on vkoul-dmaengine/next] [also build test WARNING on pci/next linux/master linus/master v5.11-rc6 next-20210125] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Gustavo-Pimentel/dmaengine-dw-edma-HDMA-support/20210204-061341 base: https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git next config: i386-randconfig-m021-20210209 (attached as .config) compiler: gcc-9 (Debian 9.3.0-15) 9.3.0 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <l...@intel.com> New smatch warnings: drivers/dma/dw-edma/dw-edma-v0-core.c:328 dw_edma_v0_core_write_chunk() warn: inconsistent indenting drivers/dma/dw-edma/dw-edma-v0-core.c:385 dw_edma_v0_core_start() warn: inconsistent indenting Old smatch warnings: drivers/dma/dw-edma/dw-edma-v0-core.c:352 dw_edma_v0_core_write_chunk() warn: inconsistent indenting vim +328 drivers/dma/dw-edma/dw-edma-v0-core.c 300 301 static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk) 302 { 303 struct dw_edma_burst *child; 304 struct dw_edma_v0_lli __iomem *lli; 305 struct dw_edma_v0_llp __iomem *llp; 306 u32 control = 0, i = 0; 307 int j; 308 309 lli = chunk->ll_region.vaddr; 310 311 if (chunk->cb) 312 control = DW_EDMA_V0_CB; 313 314 j = chunk->bursts_alloc; 315 list_for_each_entry(child, &chunk->burst->list, list) { 316 j--; 317 if (!j) 318 control |= (DW_EDMA_V0_LIE | DW_EDMA_V0_RIE); 319 320 /* Channel control */ 321 SET_LL_32(&lli[i].control, control); 322 /* Transfer size */ 323 SET_LL_32(&lli[i].transfer_size, child->sz); 324 /* SAR */ 325 #ifdef CONFIG_64BIT 326 SET_LL_64(&lli[i].sar.reg, child->sar); 327 #else /* CONFIG_64BIT */ > 328 SET_LL_32(&lli[i].sar.lsb, > lower_32_bits(child->sar)); 329 SET_LL_32(&lli[i].sar.msb, upper_32_bits(child->sar)); 330 #endif /* CONFIG_64BIT */ 331 /* DAR */ 332 #ifdef CONFIG_64BIT 333 SET_LL_64(&lli[i].dar.reg, child->dar); 334 #else /* CONFIG_64BIT */ 335 SET_LL_32(&lli[i].dar.lsb, lower_32_bits(child->dar)); 336 SET_LL_32(&lli[i].dar.msb, upper_32_bits(child->dar)); 337 #endif /* CONFIG_64BIT */ 338 i++; 339 } 340 341 llp = (void __iomem *)&lli[i]; 342 control = DW_EDMA_V0_LLP | DW_EDMA_V0_TCB; 343 if (!chunk->cb) 344 control |= DW_EDMA_V0_CB; 345 346 /* Channel control */ 347 SET_LL_32(&llp->control, control); 348 /* Linked list */ 349 #ifdef CONFIG_64BIT 350 SET_LL_64(&llp->llp.reg, chunk->ll_region.paddr); 351 #else /* CONFIG_64BIT */ 352 SET_LL_32(&llp->llp.lsb, lower_32_bits(chunk->ll_region.paddr)); 353 SET_LL_32(&llp->llp.msb, upper_32_bits(chunk->ll_region.paddr)); 354 #endif /* CONFIG_64BIT */ 355 } 356 357 void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first) 358 { 359 struct dw_edma_chan *chan = chunk->chan; 360 struct dw_edma *dw = chan->chip->dw; 361 u32 tmp; 362 363 dw_edma_v0_core_write_chunk(chunk); 364 365 if (first) { 366 /* Enable engine */ 367 SET_RW_32(dw, chan->dir, engine_en, BIT(0)); 368 /* Interrupt unmask - done, abort */ 369 tmp = GET_RW_32(dw, chan->dir, int_mask); 370 tmp &= ~FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id)); 371 tmp &= ~FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id)); 372 SET_RW_32(dw, chan->dir, int_mask, tmp); 373 /* Linked list error */ 374 tmp = GET_RW_32(dw, chan->dir, linked_list_err_en); 375 tmp |= FIELD_PREP(EDMA_V0_LINKED_LIST_ERR_MASK, BIT(chan->id)); 376 SET_RW_32(dw, chan->dir, linked_list_err_en, tmp); 377 /* Channel control */ 378 SET_CH_32(dw, chan->dir, chan->id, ch_control1, 379 (DW_EDMA_V0_CCS | DW_EDMA_V0_LLE)); 380 /* Linked list */ 381 #ifdef CONFIG_64BIT 382 SET_CH_64(dw, chan->dir, chan->id, llp.reg, 383 chunk->ll_region.paddr); 384 #else /* CONFIG_64BIT */ > 385 SET_CH_32(dw, chan->dir, chan->id, llp.lsb, 386 lower_32_bits(chunk->ll_region.paddr)); 387 SET_CH_32(dw, chan->dir, chan->id, llp.msb, 388 upper_32_bits(chunk->ll_region.paddr)); 389 #endif /* CONFIG_64BIT */ 390 } 391 /* Doorbell */ 392 SET_RW_32(dw, chan->dir, doorbell, 393 FIELD_PREP(EDMA_V0_DOORBELL_CH_MASK, chan->id)); 394 } 395 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
.config.gz
Description: application/gzip
