[PATCH v4 01/10] arm64: dts: imx8mm-nitrogen-r2: add wifi/bt chip

[Adrien Grassein]

Add usdhc3 description which corresponds to the wifi/bt chip

Signed-off-by: Adrien Grassein <adrien.grass...@gmail.com>
---
 .../boot/dts/freescale/imx8mm-nitrogen-r2.dts | 38 +++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts 
b/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts
index c0c384d76147..4a3dabeb8c85 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts
@@ -9,6 +9,24 @@
 / {
        model = "Boundary Devices i.MX8MMini Nitrogen8MM Rev2";
        compatible = "boundary,imx8mm-nitrogen8mm", "fsl,imx8mm";
+
+       reg_vref_1v8: regulator-vref-1v8 {
+               compatible = "regulator-fixed";
+               regulator-name = "vref-1v8";
+               regulator-min-microvolt = <1800000>;
+               regulator-max-microvolt = <1800000>;
+       };
+
+       reg_wlan_vmmc: regulator-wlan-vmmc {
+               compatible = "regulator-fixed";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_reg_wlan_vmmc>;
+               regulator-name = "reg_wlan_vmmc";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
 };
 
 &A53_0 {
@@ -206,6 +224,20 @@ &usdhc2 {
        status = "okay";
 };
 
+/* wlan */
+&usdhc3 {
+       bus-width = <4>;
+       sdhci-caps-mask = <0x2 0x0>;
+       non-removable;
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc3>;
+       pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+       vmmc-supply = <&reg_wlan_vmmc>;
+       vqmmc-supply = <&reg_vref_1v8>;
+       status = "okay";
+};
+
 &wdog1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_wdog>;
@@ -264,6 +296,12 @@ MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1c0
                >;
        };
 
+       pinctrl_reg_wlan_vmmc: reg-wlan-vmmcgrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x16
+               >;
+       };
+
        pinctrl_uart2: uart2grp {
                fsl,pins = <
                        MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
-- 
2.25.1