On Mon, Mar 08, 2021 at 05:59:50PM -0800, Davidlohr Bueso wrote: > 49a7d46a06c3 (powerpc: Implement smp_cond_load_relaxed()) added > busy-waiting pausing with a preferred SMT priority pattern, lowering > the priority (reducing decode cycles) during the whole loop slowpath. > > However, data shows that while this pattern works well with simple ^^^^^^^^^^^^^^^^^^^^^^ > spinlocks, queued spinlocks benefit more being kept in medium priority, > with a cpu_relax() instead, being a low+medium combo on powerpc. ... > > diff --git a/arch/powerpc/include/asm/barrier.h > b/arch/powerpc/include/asm/barrier.h > index aecfde829d5d..7ae29cfb06c0 100644 > --- a/arch/powerpc/include/asm/barrier.h > +++ b/arch/powerpc/include/asm/barrier.h > @@ -80,22 +80,6 @@ do { > \ > ___p1; \ > }) > > -#ifdef CONFIG_PPC64 Maybe it should be kept for the simple spinlock case then?
Thanks Michal > -#define smp_cond_load_relaxed(ptr, cond_expr) ({ \ > - typeof(ptr) __PTR = (ptr); \ > - __unqual_scalar_typeof(*ptr) VAL; \ > - VAL = READ_ONCE(*__PTR); \ > - if (unlikely(!(cond_expr))) { \ > - spin_begin(); \ > - do { \ > - VAL = READ_ONCE(*__PTR); \ > - } while (!(cond_expr)); \ > - spin_end(); \ > - } \ > - (typeof(*ptr))VAL; \ > -}) > -#endif > - > #ifdef CONFIG_PPC_BOOK3S_64 > #define NOSPEC_BARRIER_SLOT nop > #elif defined(CONFIG_PPC_FSL_BOOK3E) > -- > 2.26.2 >