On 09/03/21 06:35PM, Vignesh Raghavendra wrote:
> AM64 SoC has a single Octal SPI (OSPI) instance under Flash SubSystem
> (FSS). Add DT entry for the same.
>
> Signed-off-by: Vignesh Raghavendra <vigne...@ti.com>
Reviewed-by: Pratyush Yadav <p.ya...@ti.com>
> ---
> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 25 ++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> index 5f85950daef7..bcec4fa444b5 100644
> --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> @@ -402,4 +402,29 @@ sdhci1: mmc@fa00000 {
> ti,otap-del-sel-ddr50 = <0x9>;
> ti,clkbuf-sel = <0x7>;
> };
> +
> + fss: bus@fc00000 {
> + compatible = "simple-bus";
> + reg = <0x00 0x0fc00000 0x00 0x70000>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + ospi0: spi@fc40000 {
> + compatible = "ti,am654-ospi", "cdns,qspi-nor";
> + reg = <0x00 0x0fc40000 0x00 0x100>,
> + <0x05 0x00000000 0x01 0x00000000>;
> + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
> + cdns,fifo-depth = <256>;
> + cdns,fifo-width = <4>;
> + cdns,trigger-address = <0x0>;
> + #address-cells = <0x1>;
> + #size-cells = <0x0>;
> + clocks = <&k3_clks 75 6>;
> + assigned-clocks = <&k3_clks 75 6>;
> + assigned-clock-parents = <&k3_clks 75 7>;
> + assigned-clock-rates = <166666666>;
> + power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
> + };
> + };
> };
> --
> 2.30.1
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
