From: Mars Cheng <mars.ch...@mediatek.com>
This adds scpsys support for MT6765
Add subdomain support for MT6765:
isp, mm, connsys, mfg, and cam.
Signed-off-by: Mars Cheng <mars.ch...@mediatek.com>
Signed-off-by: Owen Chen <owen.c...@mediatek.com>
Signed-off-by: Macpaul Lin <macpaul....@mediatek.com>
---
drivers/soc/mediatek/mtk-scpsys.c | 91 +++++++++++++++++++++++++++++++
1 file changed, 91 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c
b/drivers/soc/mediatek/mtk-scpsys.c
index ca75b14931ec..fc8d3858f1b4 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -15,6 +15,7 @@
#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/power/mt2712-power.h>
+#include <dt-bindings/power/mt6765-power.h>
#include <dt-bindings/power/mt6797-power.h>
#include <dt-bindings/power/mt7622-power.h>
#include <dt-bindings/power/mt7623a-power.h>
@@ -750,6 +751,81 @@ static const struct scp_subdomain scp_subdomain_mt2712[] =
{
{MT2712_POWER_DOMAIN_MFG_SC2, MT2712_POWER_DOMAIN_MFG_SC3},
};
+/*
+ * MT6765 power domain support
+ */
+#define SPM_PWR_STATUS_MT6765 0x0180
+#define SPM_PWR_STATUS_2ND_MT6765 0x0184
+
+static const struct scp_domain_data scp_domain_data_mt6765[] = {
+ [MT6765_POWER_DOMAIN_VCODEC] = {
+ .name = "vcodec",
+ .sta_mask = BIT(26),
+ .ctl_offs = 0x300,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT6765_POWER_DOMAIN_ISP] = {
+ .name = "isp",
+ .sta_mask = BIT(5),
+ .ctl_offs = 0x308,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT6765_POWER_DOMAIN_MM] = {
+ .name = "mm",
+ .sta_mask = BIT(3),
+ .ctl_offs = 0x30C,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .clk_id = {CLK_MM},
+ },
+ [MT6765_POWER_DOMAIN_CONN] = {
+ .name = "conn",
+ .sta_mask = BIT(1),
+ .ctl_offs = 0x32C,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ },
+ [MT6765_POWER_DOMAIN_MFG_ASYNC] = {
+ .name = "mfg_async",
+ .sta_mask = BIT(23),
+ .ctl_offs = 0x334,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ .clk_id = {CLK_MFG},
+ },
+ [MT6765_POWER_DOMAIN_MFG] = {
+ .name = "mfg",
+ .sta_mask = BIT(4),
+ .ctl_offs = 0x338,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT6765_POWER_DOMAIN_CAM] = {
+ .name = "cam",
+ .sta_mask = BIT(25),
+ .ctl_offs = 0x344,
+ .sram_pdn_bits = GENMASK(9, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ },
+ [MT6765_POWER_DOMAIN_MFG_CORE0] = {
+ .name = "mfg_core0",
+ .sta_mask = BIT(7),
+ .ctl_offs = 0x34C,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+};
+
+static const struct scp_subdomain scp_subdomain_mt6765[] = {
+ {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_CAM},
+ {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_ISP},
+ {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_VCODEC},
+ {MT6765_POWER_DOMAIN_MFG_ASYNC, MT6765_POWER_DOMAIN_MFG},
+ {MT6765_POWER_DOMAIN_MFG, MT6765_POWER_DOMAIN_MFG_CORE0},
+};
+
/*
* MT6797 power domain support
*/
@@ -1033,6 +1109,18 @@ static const struct scp_soc_data mt2712_data = {
.bus_prot_reg_update = false,
};
+static const struct scp_soc_data mt6765_data = {
+ .domains = scp_domain_data_mt6765,
+ .num_domains = ARRAY_SIZE(scp_domain_data_mt6765),
+ .subdomains = scp_subdomain_mt6765,
+ .num_subdomains = ARRAY_SIZE(scp_subdomain_mt6765),
+ .regs = {
+ .pwr_sta_offs = SPM_PWR_STATUS_MT6765,
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6765,
+ },
+ .bus_prot_reg_update = true,
+};
+
static const struct scp_soc_data mt6797_data = {
.domains = scp_domain_data_mt6797,
.num_domains = ARRAY_SIZE(scp_domain_data_mt6797),
@@ -1088,6 +1176,9 @@ static const struct of_device_id of_scpsys_match_tbl[] = {
}, {
.compatible = "mediatek,mt2712-scpsys",
.data = &mt2712_data,
+ }, {
+ .compatible = "mediatek,mt6765-scpsys",
+ .data = &mt6765_data,
}, {
.compatible = "mediatek,mt6797-scpsys",
.data = &mt6797_data,
--
2.18.0
