Add APU power domain node to MT8192.

Signed-off-by: Flora Fu <flora...@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192-evb.dts |  7 +++++
 arch/arm64/boot/dts/mediatek/mt8192.dtsi    | 29 +++++++++++++++++++++
 2 files changed, 36 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts 
b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
index 1769f3a9b510..9e89efb3dc8a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts
@@ -65,3 +65,10 @@
 &mt6359_vrf12_ldo_reg {
        regulator-always-on;
 };
+
+&apuspm {
+       vsram-supply = <&mt6359_vsram_md_ldo_reg>;
+       power-domain@MT8192_POWER_DOMAIN_APUSYS_TOP {
+               domain-supply = <&mt6359_vproc1_buck_reg>;
+       };
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index b1467ccbe5aa..546c058ef560 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -11,6 +11,7 @@
 #include <dt-bindings/memory/mt8192-larb-port.h>
 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
 #include <dt-bindings/power/mt8192-power.h>
+#include <dt-bindings/power/mt8192-apu-power.h>
 
 / {
        compatible = "mediatek,mt8192";
@@ -1033,6 +1034,34 @@
                        #clock-cells = <1>;
                };
 
+               apuspm: power-domain@190f0000 {
+                       compatible = "mediatek,mt8192-apu-pm", "syscon";
+                       reg = <0 0x190f0000 0 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       #power-domain-cells = <1>;
+                       mediatek,scpsys = <&scpsys>;
+                       mediatek,apu_conn = <&apu_conn>;
+                       mediatek,apu_vcore = <&apu_vcore>;
+
+                       power-domain@MT8192_POWER_DOMAIN_APUSYS_TOP {
+                               reg = <MT8192_POWER_DOMAIN_APUSYS_TOP>;
+                               #power-domain-cells = <0>;
+                               clocks = <&topckgen CLK_TOP_DSP_SEL>,
+                                        <&topckgen CLK_TOP_IPU_IF_SEL>,
+                                        <&clk26m>,
+                                        <&topckgen CLK_TOP_UNIVPLL_D6_D2>;
+                               clock-names = "clk_top_conn",
+                                             "clk_top_ipu_if",
+                                             "clk_off",
+                                             "clk_on_default";
+                               assigned-clocks = <&topckgen CLK_TOP_DSP_SEL>,
+                                                 <&topckgen 
CLK_TOP_IPU_IF_SEL>;
+                               assigned-clock-parents = <&topckgen 
CLK_TOP_UNIVPLL_D6_D2>,
+                                                        <&topckgen 
CLK_TOP_UNIVPLL_D6_D2>;
+                       };
+               };
+
                larb13: larb@1a001000 {
                        compatible = "mediatek,mt8192-smi-larb";
                        reg = <0 0x1a001000 0 0x1000>;
-- 
2.18.0

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