On 4/9/2021 12:41 PM, Borislav Petkov wrote:
> On Tue, Apr 06, 2021 at 10:50:00AM -0500, Ramakrishna Saripalli wrote:
>> diff --git a/arch/x86/include/asm/cpufeatures.h
>> b/arch/x86/include/asm/cpufeatures.h
>> index cc96e26d69f7..21e7f8d0d7d9 100644
>> --- a/arch/x86/include/asm/cpufeatures.h
>> +++ b/arch/x86/include/asm/cpufeatures.h
>> @@ -201,7 +201,7 @@
>> #define X86_FEATURE_INVPCID_SINGLE ( 7*32+ 7) /* Effectively INVPCID &&
>> CR4.PCIDE=1 */
>> #define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */
>> #define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface
>> */
>> -/* FREE! ( 7*32+10) */
>> +#define X86_FEATURE_PSFD ( 7*32+10) /* Predictive Store Forward
>> Disable */
>
> You don't need this one...
Boris, I added this bit so we could detect later that PSF is supported.
But since PSF is AMD specific for now, I guess I will go along with your
suggestions.
>
>> #define X86_FEATURE_PTI ( 7*32+11) /* Kernel Page Table
>> Isolation enabled */
>> #define X86_FEATURE_RETPOLINE ( 7*32+12) /* "" Generic
>> Retpoline mitigation for Spectre variant 2 */
>> #define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* "" AMD Retpoline
>> mitigation for Spectre variant 2 */
>> @@ -309,6 +309,7 @@
>> #define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative
>> Store Bypass Disable */
>> #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized
>> Speculative Store Bypass Disable */
>> #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative
>> Store Bypass is fixed in hardware. */
>> +#define X86_FEATURE_AMD_PSFD (13*32+28) /* "" Predictive
>> Store Forward Disable */
>
> ... when you have this one. And this one is AMD-specific so you can just
> as well call it X86_FEATURE_PSFD and remove the "".
Ok
>
>>
>> /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14
>> */
>> #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */
>> @@ -428,5 +429,6 @@
>> #define X86_BUG_TAA X86_BUG(22) /* CPU is affected by TSX
>> Async Abort(TAA) */
>> #define X86_BUG_ITLB_MULTIHIT X86_BUG(23) /* CPU may incur
>> MCE during certain page attribute changes */
>> #define X86_BUG_SRBDS X86_BUG(24) /* CPU may leak RNG
>> bits if not mitigated */
>> +#define X86_BUG_PSF X86_BUG(25) /* CPU is affected by
>> Predictive Store Forwarding attack */
>
> And I think you don't need this one either if we do a "light" controls
> thing but lemme look at the rest first.
>
Ok.
> Thx.
>
