On Wed, Apr 14, 2021 at 08:39:33PM +0800, Guo Ren wrote: > I've tested it on csky SMP*4 hw (860) & riscv SMP*4 hw (c910) and it's okay.
W00t :-) > Hope you can keep > typedef struct { > union { > atomic_t lock; > struct __raw_tickets { > #ifdef __BIG_ENDIAN > u16 next; > u16 owner; > #else > u16 owner; > u16 next; > #endif > } tickets; > }; > } arch_spinlock_t; > > Using owner & next is much more readable. That almost doubles the line-count of the thing ;-) > > + * It further assumes atomic_*_release() + atomic_*_acquire() is RCpc and > > hence > > + * uses atomic_fetch_add() which is SC to create an RCsc lock. This ^^^ then vvv > > +static __always_inline void ticket_lock(arch_spinlock_t *lock) > > +{ > > + u32 val = atomic_fetch_add(1<<16, lock); /* SC, gives us RCsc */ > atomic_fetch_add_acquire ? Then we must rely on the arch to implement RCsc atomics. And I for one can never tell wth Risc-V actually does. > > +static __always_inline int ticket_is_locked(arch_spinlock_t *lock) > > +{ > > + u32 val = atomic_read(lock); > > + > > + return ((val >> 16) != (val & 0xffff)); > I perfer: > return !arch_spin_value_unlocked(READ_ONCE(*lock)); > > +} > > +} > > + > > +static __always_inline int ticket_value_unlocked(arch_spinlock_t lock) > > +{ > > + return !ticket_is_locked(&lock); > Are you sure to let ticket_is_locked->atomic_read(lock) again, the > lock has contained all information? > > return lock.tickets.owner == lock.tickets.next; Yeah, I wrote then the wrong way around. Couldn't be bothered to go back when I figured it out. > > + > > +static __always_inline int ticket_is_contended(arch_spinlock_t *lock) > > +{ > > + u32 val = atomic_read(lock); > > + > > + return (s16)((val >> 16) - (val & 0xffff)) > 1; > How big-endian ? How not? Endian-ness only matters when you go poke at sub-words, which the above does not. Only ticket_unlock() does and cares about that.