From: Michal Simek <[EMAIL PROTECTED]>
Signed-off-by: Michal Simek <[EMAIL PROTECTED]>
---
arch/microblaze/platform/generic/system.dts | 137 +++++++++++++++++++++++++++
1 files changed, 137 insertions(+), 0 deletions(-)
create mode 100644 arch/microblaze/platform/generic/system.dts
diff --git a/arch/microblaze/platform/generic/system.dts
b/arch/microblaze/platform/generic/system.dts
new file mode 100644
index 0000000..91eac31
--- /dev/null
+++ b/arch/microblaze/platform/generic/system.dts
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal SIMEK <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * CAUTION: This file is automatically generated by libgen.
+ * Version: Xilinx EDK 9.2 EDK_Jm.16
+ * Generate by U-BOOT v4.00.b
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ibm,opb";
+ model = "testing";
+ DDR_SDRAM_32Mx16: [EMAIL PROTECTED] {
+ device_type = "memory";
+ reg = < 44000000 2000000 >;
+ } ;
+ chosen {
+ bootargs = "root=mtdblock0";
+ } ;
+ cpus {
+ #address-cells = <1>;
+ #cpus = <1>;
+ #size-cells = <0>;
+ microblaze,[EMAIL PROTECTED] {
+ clock-frequency = <3f940ab>;
+ d-cache-baseaddr = <44000000>;
+ d-cache-highaddr = <47ffffff>;
+ d-cache-line-size = <10>;
+ d-cache-size = <2000>;
+ device_type = "cpu";
+ i-cache-baseaddr = <44000000>;
+ i-cache-highaddr = <47ffffff>;
+ i-cache-line-size = <10>;
+ i-cache-size = <2000>;
+ reg = <0>;
+ timebase-frequency = <3f940ab>;
+ xlnx,addr-tag-bits = <d>;
+ xlnx,allow-dcache-wr = <1>;
+ xlnx,allow-icache-wr = <1>;
+ xlnx,cache-byte-size = <2000>;
+ xlnx,d-lmb = <1>;
+ xlnx,d-opb = <1>;
+ xlnx,data-size = <20>;
+ xlnx,dcache-addr-tag = <d>;
+ xlnx,dcache-byte-size = <2000>;
+ xlnx,dcache-line-len = <4>;
+ xlnx,dcache-use-fsl = <1>;
+ xlnx,debug-enabled = <1>;
+ xlnx,div-zero-exception = <0>;
+ xlnx,dopb-bus-exception = <0>;
+ xlnx,dynamic-bus-sizing = <1>;
+ xlnx,edge-is-positive = <1>;
+ xlnx,fpu-exception = <0>;
+ xlnx,fsl-data-size = <20>;
+ xlnx,fsl-links = <1>;
+ xlnx,i-lmb = <1>;
+ xlnx,i-opb = <1>;
+ xlnx,icache-line-len = <4>;
+ xlnx,icache-use-fsl = <1>;
+ xlnx,ill-opcode-exception = <0>;
+ xlnx,instance = "microblaze_0";
+ xlnx,interrupt-is-edge = <0>;
+ xlnx,iopb-bus-exception = <0>;
+ xlnx,number-of-pc-brk = <2>;
+ xlnx,number-of-rd-addr-brk = <0>;
+ xlnx,number-of-wr-addr-brk = <0>;
+ xlnx,opcode-0x0-illegal = <0>;
+ xlnx,pvr = <2>;
+ xlnx,pvr-user1 = <0>;
+ xlnx,pvr-user2 = <0>;
+ xlnx,reset-msr = <0>;
+ xlnx,sco = <0>;
+ xlnx,unaligned-exceptions = <0>;
+ xlnx,use-barrel = <1>;
+ xlnx,use-dcache = <1>;
+ xlnx,use-div = <1>;
+ xlnx,use-fpu = <0>;
+ xlnx,use-hw-mul = <1>;
+ xlnx,use-icache = <1>;
+ xlnx,use-msr-instr = <1>;
+ xlnx,use-pcmp-instr = <1>;
+ } ;
+ } ;
+ opb_v20 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "xlnx,opb-v20-1.10.c", "xlnx,opb-v20";
+ RS232_DTE: [EMAIL PROTECTED] {
+ compatible = "xlnx,opb-uartlite-1.00.b",
"xlnx,opb-uartlite", "xilinx,uartlite";
+ interrupt-parent = <&opb_intc_0>;
+ interrupts = < 2 0 >;
+ reg = < 40600000 10000 >;
+ xlnx,baudrate = <1c200>;
+ xlnx,clk-freq = <3f940ab>;
+ xlnx,data-bits = <8>;
+ xlnx,odd-parity = <0>;
+ xlnx,use-parity = <0>;
+ } ;
+ opb_intc_0: [EMAIL PROTECTED] {
+ #interrupt-cells = <2>;
+ compatible = "xlnx,opb-intc-1.00.c", "xlnx,opb-intc";
+ interrupt-controller ;
+ reg = < 41200000 10000 >;
+ xlnx,num-intr-inputs = <5>;
+ } ;
+ opb_timer_0: [EMAIL PROTECTED] {
+ compatible = "xlnx,opb-timer-1.00.b", "xlnx,opb-timer";
+ interrupt-parent = <&opb_intc_0>;
+ interrupts = < 0 0 >;
+ reg = < 41c00000 10000 >;
+ xlnx,count-width = <20>;
+ xlnx,gen0-assert = <1>;
+ xlnx,gen1-assert = <1>;
+ xlnx,one-timer-only = <1>;
+ xlnx,trig0-assert = <1>;
+ xlnx,trig1-assert = <1>;
+ } ;
+ } ;
+} ;
--
1.5.4.rc4.14.g6fc74
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