On Sun, 13 Apr 2025 17:52:11 -0500
Ira Weiny <ira.we...@intel.com> wrote:
> Additional DCD partition (AKA region) information is contained in the
> DSMAS CDAT tables, including performance, read only, and shareable
> attributes.
>
> Match DCD partitions with DSMAS tables and store the meta data.
>
> Signed-off-by: Ira Weiny <ira.we...@intel.com>
> diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
> index 866a423d6125..c589d8a330bb 100644
> --- a/drivers/cxl/core/mbox.c
> +++ b/drivers/cxl/core/mbox.c
> @@ -1321,6 +1321,7 @@ static int cxl_dc_check(struct device *dev, struct
> cxl_dc_partition_info *part_a
> part_array[index].start = le64_to_cpu(dev_part->base);
> part_array[index].size = le64_to_cpu(dev_part->decode_length);
> part_array[index].size *= CXL_CAPACITY_MULTIPLIER;
> + part_array[index].handle = le32_to_cpu(dev_part->dsmad_handle) & 0xFF;
Perhaps a comment on this. Or a check that it is representable in
CDAT (where we only have the one byte) and a print + fail to carry on if not?
> len = le64_to_cpu(dev_part->length);
> blk_size = le64_to_cpu(dev_part->block_size);
>
> @@ -1453,6 +1454,7 @@ int cxl_dev_dc_identify(struct cxl_mailbox *mbox,
> /* Return 1st partition */
> dc_info->start = partitions[0].start;
> dc_info->size = partitions[0].size;
> + dc_info->handle = partitions[0].handle;
> dev_dbg(dev, "Returning partition 0 %zu size %zu\n",
> dc_info->start, dc_info->size);
>
> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index 057933128d2c..96d8edaa5003 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -104,6 +104,7 @@ struct cxl_dpa_info {
> struct cxl_dpa_part_info {
> struct range range;
> enum cxl_partition_mode mode;
> + u8 handle;
> } part[CXL_NR_PARTITIONS_MAX];
> int nr_partitions;
> };
> @@ -387,12 +388,14 @@ enum cxl_devtype {
> * @coord: QoS performance data (i.e. latency, bandwidth)
> * @cdat_coord: raw QoS performance data from CDAT
> * @qos_class: QoS Class cookies
> + * @shareable: Is the range sharable
> */
> struct cxl_dpa_perf {
> struct range dpa_range;
> struct access_coordinate coord[ACCESS_COORDINATE_MAX];
> struct access_coordinate cdat_coord[ACCESS_COORDINATE_MAX];
> int qos_class;
> + bool shareable;
It feels a bit odd to have this in the dpa_perf structure as not really
a performance thing but I guess this is only convenient place to stash it.
> };
>
> /**
> @@ -400,11 +403,13 @@ struct cxl_dpa_perf {
> * @res: shortcut to the partition in the DPA resource tree (cxlds->dpa_res)
> * @perf: performance attributes of the partition from CDAT
> * @mode: operation mode for the DPA capacity, e.g. ram, pmem, dynamic...
> + * @handle: DMASS handle intended to represent this partition
DSMAS ?
> */
> struct cxl_dpa_partition {
> struct resource res;
> struct cxl_dpa_perf perf;
> enum cxl_partition_mode mode;
> + u8 handle;
> };
>
> /**
> @@ -881,6 +886,7 @@ struct cxl_mem_dev_info {
> struct cxl_dc_partition_info {
> size_t start;
> size_t size;
> + u8 handle;
> };
>
> int cxl_dev_dc_identify(struct cxl_mailbox *mbox,
>
