On 10/21/2025 11:38 PM, Luca Weiss wrote:
> The 'Agera' PLLs (with clk_agera_pll_configure) do not take some of the
> parameters that are provided in the vendor driver. Instead the upstream
> configuration should provide the final user_ctl value that is written to
> the USER_CTL register.
>
> Fix the config so that the PLL is configured correctly, and fixes
> CAMCC_MCLK* being stuck off.
>
> Fixes: 80f5451d9a7c ("clk: qcom: Add camera clock controller driver for
> SM6350")
> Suggested-by: Taniya Das <[email protected]>
> Signed-off-by: Luca Weiss <[email protected]>
> ---
> drivers/clk/qcom/camcc-sm6350.c | 6 +-----
> 1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/drivers/clk/qcom/camcc-sm6350.c b/drivers/clk/qcom/camcc-sm6350.c
> index 8aac97d29ce3..87806392a59d 100644
> --- a/drivers/clk/qcom/camcc-sm6350.c
> +++ b/drivers/clk/qcom/camcc-sm6350.c
> @@ -145,15 +145,11 @@ static struct clk_alpha_pll_postdiv camcc_pll1_out_even
> = {
> static const struct alpha_pll_config camcc_pll2_config = {
> .l = 0x64,
> .alpha = 0x0,
> - .post_div_val = 0x3 << 8,
> - .post_div_mask = 0x3 << 8,
> - .aux_output_mask = BIT(1),
> - .main_output_mask = BIT(0),
> - .early_output_mask = BIT(3),
> .config_ctl_val = 0x20000800,
> .config_ctl_hi_val = 0x400003d2,
> .test_ctl_val = 0x04000400,
> .test_ctl_hi_val = 0x00004000,
> + .user_ctl_val = 0x0000030b,
> };
>
> static struct clk_alpha_pll camcc_pll2 = {
>
Reviewed-by: Taniya Das <[email protected]>
--
Thanks,
Taniya Das
