[PATCH v4 9/9] selftests: riscv: verify syscalls discard vector context

[Sergey Matyukevich]

Add a test to v_ptrace test suite to verify that vector csr registers
are clobbered on syscalls.

Signed-off-by: Sergey Matyukevich <geoma...@gmail.com>
---
 .../testing/selftests/riscv/vector/v_ptrace.c | 107 ++++++++++++++++++
 1 file changed, 107 insertions(+)

diff --git a/tools/testing/selftests/riscv/vector/v_ptrace.c 
b/tools/testing/selftests/riscv/vector/v_ptrace.c
index fb371a42de15..d4e947c33f75 100644
--- a/tools/testing/selftests/riscv/vector/v_ptrace.c
+++ b/tools/testing/selftests/riscv/vector/v_ptrace.c
@@ -183,6 +183,113 @@ TEST(ptrace_v_early_debug)
        }
 }
 
+TEST(ptrace_v_syscall_clobbering)
+{
+       unsigned long vlenb;
+       pid_t pid;
+
+       if (!is_vector_supported())
+               SKIP(return, "Vector not supported");
+
+       asm volatile("csrr %[vlenb], vlenb" : [vlenb] "=r"(vlenb));
+
+       chld_lock = 1;
+       pid = fork();
+       ASSERT_LE(0, pid)
+               TH_LOG("fork: %m");
+
+       if (pid == 0) {
+               unsigned long vl;
+
+               while (chld_lock == 1)
+                       asm volatile("" : : "g"(chld_lock) : "memory");
+
+               asm(".option arch, +zve32x\n");
+               asm(".option arch, +c\n");
+               asm volatile("vsetvli %[new_vl], x0, e16, m2, tu, mu\n"
+                            : [new_vl] "=r"(vl)
+                            :
+                            :);
+
+               while (1) {
+                       asm volatile ("c.ebreak");
+                       sleep(0);
+               }
+       } else {
+               struct __riscv_v_regset_state *regset_data;
+               struct user_regs_struct regs;
+               size_t regset_size;
+               struct iovec iov;
+               int status;
+
+               /* attach */
+
+               ASSERT_EQ(0, ptrace(PTRACE_ATTACH, pid, NULL, NULL));
+               ASSERT_EQ(pid, waitpid(pid, &status, 0));
+               ASSERT_TRUE(WIFSTOPPED(status));
+
+               /* unlock */
+
+               ASSERT_EQ(0, ptrace(PTRACE_POKEDATA, pid, &chld_lock, 0));
+
+               /* resume and wait for the 1st c.ebreak */
+
+               ASSERT_EQ(0, ptrace(PTRACE_CONT, pid, NULL, NULL));
+               ASSERT_EQ(pid, waitpid(pid, &status, 0));
+               ASSERT_TRUE(WIFSTOPPED(status));
+
+               /* read tracee vector csr regs using ptrace GETREGSET */
+
+               regset_size = sizeof(*regset_data) + vlenb * 32;
+               regset_data = calloc(1, regset_size);
+
+               iov.iov_base = regset_data;
+               iov.iov_len = regset_size;
+
+               ASSERT_EQ(0, ptrace(PTRACE_GETREGSET, pid, NT_RISCV_VECTOR, 
&iov));
+
+               /* verify initial vsetvli settings */
+
+               EXPECT_EQ(regset_data->vlenb, regset_data->vl);
+               EXPECT_EQ(9UL, regset_data->vtype);
+               EXPECT_EQ(vlenb, regset_data->vlenb);
+               EXPECT_EQ(0UL, regset_data->vstart);
+               EXPECT_EQ(0UL, regset_data->vcsr);
+
+               /* skip 1st c.ebreak, then resume and wait for the 2nd c.ebreak 
*/
+
+               iov.iov_base = &regs;
+               iov.iov_len = sizeof(regs);
+
+               ASSERT_EQ(0, ptrace(PTRACE_GETREGSET, pid, NT_PRSTATUS, &iov));
+               regs.pc += 2;
+               ASSERT_EQ(0, ptrace(PTRACE_SETREGSET, pid, NT_PRSTATUS, &iov));
+
+               ASSERT_EQ(0, ptrace(PTRACE_CONT, pid, NULL, NULL));
+               ASSERT_EQ(pid, waitpid(pid, &status, 0));
+               ASSERT_TRUE(WIFSTOPPED(status));
+
+               /* read tracee vtype using ptrace GETREGSET */
+
+               iov.iov_base = regset_data;
+               iov.iov_len = regset_size;
+
+               ASSERT_EQ(0, ptrace(PTRACE_GETREGSET, pid, NT_RISCV_VECTOR, 
&iov));
+
+               /* verify that V state is illegal after syscall */
+
+               EXPECT_EQ((1UL << (__riscv_xlen - 1)), regset_data->vtype);
+               EXPECT_EQ(vlenb, regset_data->vlenb);
+               EXPECT_EQ(0UL, regset_data->vstart);
+               EXPECT_EQ(0UL, regset_data->vcsr);
+               EXPECT_EQ(0UL, regset_data->vl);
+
+               /* cleanup */
+
+               ASSERT_EQ(0, kill(pid, SIGKILL));
+       }
+}
+
 FIXTURE(v_csr_invalid)
 {
 };
-- 
2.51.0