Re: [PATCH RFC 1/8] media: qcom: camss: csiphy-3ph: Add Gen2 v1.1 MIPI CSI-2 CPHY init

[Vladimir Zapolskiy]

On 11/9/25 11:39, David Heidelberg via B4 Relay wrote:

From: Casey Connolly <casey.conno...@linaro.org>

Add a PHY configuration sequence for the sdm845 which uses a Qualcomm
Gen 2 version 1.1 CSI-2 PHY.

The PHY can be configured as two phase or three phase in C-PHY or D-PHY
mode. This configuration supports three-phase C-PHY mode.

Signed-off-by: Casey Connolly <casey.conno...@linaro.org>
Signed-off-by: David Heidelberg <da...@ixit.cz>
---
  .../platform/qcom/camss/camss-csiphy-3ph-1-0.c     | 64 ++++++++++++++++++++++
  1 file changed, 64 insertions(+)

diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c 
b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index 619abbf607813..f28c32d1a4ec5 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -144,6 +144,7 @@ csiphy_lane_regs lane_regs_sa8775p[] = {
  };

/* GEN2 1.0 2PH */

+/* 5 entries: clock + 4 lanes */
  static const struct
  csiphy_lane_regs lane_regs_sdm845[] = {
        {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -218,6 +219,69 @@ csiphy_lane_regs lane_regs_sdm845[] = {
        {0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
  };

+/* GEN2 1.0 3PH */

+/* 3 entries: 3 lanes (C-PHY) */
+static const struct
+csiphy_lane_regs lane_regs_sdm845_3ph[] = {
+       {0x015C, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x0168, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x016C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x010C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+       {0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
+       {0x0114, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x0150, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x0118, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x011C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x0120, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x0124, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x012C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x0144, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x01CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x0164, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x01DC, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x035C, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x0368, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x036C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x030C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+       {0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
+       {0x0314, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x0350, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x0318, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x031C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x0320, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x0324, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x032C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x0344, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x03CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x0364, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x03DC, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x055C, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},

You may find it be more structured, if the array is split between
0x01zz, 0x03zz and 0x05zz blocks by new lines, each of those three
blocks is a configuration of one of three lanes in total.

+       {0x0568, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x056C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x050C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+       {0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
+       {0x0514, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x0550, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x0518, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x051C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x0520, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x0524, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x0528, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x052C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x0544, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x0560, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x05CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x0564, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+       {0x05DC, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS},
+};
+
  /* GEN2 1.1 2PH */
  static const struct
  csiphy_lane_regs lane_regs_sc8280xp[] = {

Reviewed-by: Vladimir Zapolskiy <vladimir.zapols...@linaro.org>

--
Best wishes,
Vladimir