On 1/16/26 3:50 PM, Luca Weiss wrote:
> In order to set the pinctrl for the individual CTS, RTS, TX and RX pins,
> split up the pinctrl configuration into 4 nodes so that boards can set
> some properties separately.
>
> Signed-off-by: Luca Weiss <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/milos.dtsi | 26 +++++++++++++++-----------
> 1 file changed, 15 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi
> b/arch/arm64/boot/dts/qcom/milos.dtsi
> index 0f69deabb60c..024e1c9992fe 100644
> --- a/arch/arm64/boot/dts/qcom/milos.dtsi
> +++ b/arch/arm64/boot/dts/qcom/milos.dtsi
> @@ -915,7 +915,7 @@ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
> interconnect-names = "qup-core",
> "qup-config";
>
> - pinctrl-0 = <&qup_uart11_default>,
> <&qup_uart11_cts_rts>;
> + pinctrl-0 = <&qup_uart11_cts>,
> <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
> pinctrl-names = "default";
>
> status = "disabled";
> @@ -1835,20 +1835,24 @@ qup_uart5_default: qup-uart5-default-state {
> bias-disable;
> };
>
> - qup_uart11_default: qup-uart11-default-state {
> - /* TX, RX */
> - pins = "gpio50", "gpio51";
> + qup_uart11_cts: qup-uart11-cts-state {
> + pins = "gpio48";
> function = "qup1_se4";
> - drive-strength = <2>;
> - bias-pull-up;
> };
I think the best setup is
qup_uart11_default: foo-state {
qup_uart11_tx: bar-pins {
...
};
};
qup_uart11_cts_rts: foo-state {
qup_uart11_rts: bar-pins {
...
};
};
Since there's a lower amount of references at the user (default vs
cts/rts still makes sense as that's a wiring difference) but we still
keep a label for customizing the properties
Konrad
