Hi Sergey, On Sun, Dec 14, 2025 at 10:35 AM Sergey Matyukevich <[email protected]> wrote: > > This patch series suggests fixes for several corner cases in the RISC-V > vector ptrace implementation: > > - init vector context with proper vlenb, to avoid reading zero vlenb > by an early attached debugger > > - follow gdbserver expectations and return ENODATA instead of EINVAL > if vector extension is supported but not yet activated for the > traced process > > - validate input vector csr registers in ptrace, to maintain an accurate > view of the tracee's vector context across multiple halt/resume > debug cycles > > For detailed description see the appropriate commit messages. A new test > suite validate_v_ptrace is added to the tools/testing/selftests/riscv/vector > to verify some of the vector ptrace functionality and corner cases. > > So far tested on the following platforms: > - test in QEMU rv32/rv64 > - test on c908 (BananaPi CanMV K230D Zero) > - test on c906 (MangoPi MQ Pro) > > Previous versions: > - v4: > https://lore.kernel.org/linux-riscv/[email protected]/T/#u > - v3: > https://lore.kernel.org/linux-riscv/[email protected]/T/#u > - v2: > https://lore.kernel.org/linux-riscv/[email protected]/T/#u > - v1: > https://lore.kernel.org/linux-riscv/[email protected]/T/#u > > Changes in v5: > - add support and minimal set of tests for XTheadVector > > Changes in v4: > The form 'vsetvli x0, x0, ...' can only be used if VLMAX remains > unchanged, see spec 6.2. This condition was not met by the initial > values in the selftests w.r.t. the initial zeroed context. QEMU accepted > such values, but actual hardware (c908, BananaPi CanMV Zero board) did > not, setting vill. So fix the selftests after testing on hardware: > - replace 'vsetvli x0, x0, ...' by 'vsetvli rd, x0, ...' > - fixed instruction returns VLMAX, so use it in checks as well > - replace fixed vlenb == 16 in the syscall test > > Changes in v3: > Address the review comments by Andy Chiu and rework the approach: > - drop forced vector context save entirely > - perform strict validation of vector csr regs in ptrace > > Changes in v2: > - add thread_info flag to allow to force vector context save > - force vector context save after vector ptrace to ensure valid vector > context in the next ptrace operations > - force vector context save on the first context switch after vector > context init to get proper vlenb > > --- > > Ilya Mamay (1): > riscv: ptrace: return ENODATA for inactive vector extension > > Sergey Matyukevich (8): > riscv: vector: init vector context with proper vlenb > riscv: csr: define vtype register elements > riscv: ptrace: validate input vector csr registers > selftests: riscv: test ptrace vector interface > selftests: riscv: verify initial vector state with ptrace > selftests: riscv: verify syscalls discard vector context > selftests: riscv: verify ptrace rejects invalid vector csr inputs > selftests: riscv: verify ptrace accepts valid vector csr values > > arch/riscv/include/asm/csr.h | 17 + > arch/riscv/kernel/ptrace.c | 98 +- > arch/riscv/kernel/vector.c | 12 +- > .../testing/selftests/riscv/vector/.gitignore | 2 + > tools/testing/selftests/riscv/vector/Makefile | 10 +- > .../selftests/riscv/vector/v_helpers.c | 23 + > .../selftests/riscv/vector/v_helpers.h | 2 + > .../riscv/vector/validate_v_ptrace.c | 919 ++++++++++++++++++ > 8 files changed, 1075 insertions(+), 8 deletions(-) > create mode 100644 tools/testing/selftests/riscv/vector/validate_v_ptrace.c > > > base-commit: 8f0b4cce4481fb22653697cced8d0d04027cb1e8 > -- > 2.52.0 >
For the series: Tested-by: Andy Chiu <[email protected]> (on qemu rv64gcv) Thanks, Andy
