The MDSS resets were left undescribed. Add them to allow resetting the
display subsystem, which is necessary to avoid issues caused by state
left over from the bootloader on various platforms.
Fixes: 6e87c8f07407 ("clk: qcom: Add display clock controller driver for
SM6125")
Reviewed-by: Dmitry Baryshkov <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Val Packett <[email protected]>
---
drivers/clk/qcom/dispcc-sm6125.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/clk/qcom/dispcc-sm6125.c b/drivers/clk/qcom/dispcc-sm6125.c
index 851d38a487d3..2c67abcfef12 100644
--- a/drivers/clk/qcom/dispcc-sm6125.c
+++ b/drivers/clk/qcom/dispcc-sm6125.c
@@ -17,6 +17,7 @@
#include "clk-regmap.h"
#include "common.h"
#include "gdsc.h"
+#include "reset.h"
enum {
P_BI_TCXO,
@@ -607,6 +608,10 @@ static struct clk_branch disp_cc_xo_clk = {
},
};
+static const struct qcom_reset_map disp_cc_sm6125_resets[] = {
+ [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
+};
+
static struct gdsc mdss_gdsc = {
.gdscr = 0x3000,
.pd = {
@@ -663,6 +668,8 @@ static const struct qcom_cc_desc disp_cc_sm6125_desc = {
.config = &disp_cc_sm6125_regmap_config,
.clks = disp_cc_sm6125_clocks,
.num_clks = ARRAY_SIZE(disp_cc_sm6125_clocks),
+ .resets = disp_cc_sm6125_resets,
+ .num_resets = ARRAY_SIZE(disp_cc_sm6125_resets),
.gdscs = disp_cc_sm6125_gdscs,
.num_gdscs = ARRAY_SIZE(disp_cc_sm6125_gdscs),
};
--
2.52.0
