On 1/8/26 11:21 AM, Konrad Dybcio wrote:
From: Konrad Dybcio <[email protected]>
Now that the highest_bank_bit value is retrieved from the running
system and the global config has been part of the tree for a couple
of releases, there is no reason to keep any hardcoded values inside
the GPU driver.
[…]
- if (adreno_is_a610(gpu)) {
- cfg->highest_bank_bit = 13;
- cfg->ubwc_swizzle = 0x7;
- }
Just noticed that the SoCs with A610 (SM6115/SM6125) have
.highest_bank_bit = 14 in drivers/soc/qcom/ubwc_config.c unlike this 13
value here.
Could this have been the cause of the corruption I saw on SM6115
initially? [1]
What's really strange though is that I wanted to test this now, but I
removed the FD_MESA_DEBUG=noubwc workaround that solved it initially…
and the corruption *did not* come back so I can't even repro it to
confirm that this would fix it o.0
[1]:
https://cache.treehouse.systems/media_attachments/files/116/083/578/070/293/038/original/9b8e73e15bed644f.jpg
