On Sun, Mar 08, 2026 at 03:19:20PM -0300, Jason Gunthorpe wrote: > On Sat, Mar 07, 2026 at 06:49:56PM +0200, Leon Romanovsky wrote: > > > -This attribute indicates the CPU will not dirty any cacheline overlapping > > this > > -DMA_FROM_DEVICE/DMA_BIDIRECTIONAL buffer while it is mapped. This allows > > -multiple small buffers to safely share a cacheline without risk of data > > -corruption, suppressing DMA debug warnings about overlapping mappings. > > -All mappings sharing a cacheline should have this attribute. > > +DMA_ATTR_CPU_CACHE_OVERLAP > > This is a very specific and well defined use case that allows some cache > flushing behaviors to work only under the promise that the CPU doesn't > touch the memory to cause cache inconsistencies. > > > +Another valid use case is on systems that are CPU-coherent and do not use > > +SWIOTLB, where the caller can guarantee that no cache maintenance > > operations > > +(such as flushes) will be performed that could overwrite shared cache > > lines. > > This is something completely unrelated.
I disagree. The situation is equivalent in that callers guarantee the CPU cache will not be overwritten. For the RDMA case, this results in the same behavior as with virtio. For our case, it addresses and clears the debug warnings. > > What I would really like is a new DMA_ATTR_REQUIRE_COHERENT which > fails any mappings requests that would use any SWIOTLB or cache > flushing. You are proposing something orthogonal that operates at a different layer (DMA mapping). However, for DMA debugging, your new attribute will be equivalent to DMA_ATTR_CPU_CACHE_OVERLAP. Thanks
